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ram: Add driver for MPC83xx

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Add a RAM driver for the MPC83xx architecture.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six 2018-08-06 10:23:30 +02:00 committed by Simon Glass
parent 0f1caa9880
commit e40615565d
8 changed files with 1593 additions and 0 deletions
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314
Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt Normal file
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@ -0,0 +1,314 @@
MPC83xx RAM controller
This driver supplies support for the embedded RAM controller on MCP83xx-series
SoCs.
For static configuration mode, each controller node should have child nodes
describing the actual RAM modules installed.
Controller node
===============
Required properties:
- compatible: Must be "fsl,mpc83xx-mem-controller"
- reg: The address of the RAM controller's register space
- #address-cells: Must be 2
- #size-cells: Must be 1
- driver_software_override: DDR driver software override is enabled (1) or
disabled (0)
- p_impedance_override: DDR driver software p-impedance override; possible
values:
* DSO_P_IMPEDANCE_HIGHEST_Z
* DSO_P_IMPEDANCE_MUCH_HIGHER_Z
* DSO_P_IMPEDANCE_HIGHER_Z
* DSO_P_IMPEDANCE_NOMINAL
* DSO_P_IMPEDANCE_LOWER_Z
- n_impedance_override: DDR driver software n-impedance override; possible
values:
* DSO_N_IMPEDANCE_HIGHEST_Z
* DSO_N_IMPEDANCE_MUCH_HIGHER_Z
* DSO_N_IMPEDANCE_HIGHER_Z
* DSO_N_IMPEDANCE_NOMINAL
* DSO_N_IMPEDANCE_LOWER_Z
- odt_termination_value: ODT termination value for I/Os; possible values:
* ODT_TERMINATION_75_OHM
* ODT_TERMINATION_150_OHM
- ddr_type: Selects voltage level for DDR pads; possible
values:
* DDR_TYPE_DDR2_1_8_VOLT
* DDR_TYPE_DDR1_2_5_VOLT
- mvref_sel: Determine where MVREF_SEL signal is generated;
possible values:
* MVREF_SEL_EXTERNAL
* MVREF_SEL_INTERNAL_GVDD
- m_odr: Disable memory transaction reordering; possible
values:
* M_ODR_ENABLE
* M_ODR_DISABLE
- clock_adjust: Clock adjust; possible values:
* CLOCK_ADJUST_025
* CLOCK_ADJUST_05
* CLOCK_ADJUST_075
* CLOCK_ADJUST_1
- ext_refresh_rec: Extended refresh recovery time; possible values:
0, 16, 32, 48, 64, 80, 96, 112
- read_to_write: Read-to-write turnaround; possible values:
0, 1, 2, 3
- write_to_read: Write-to-read turnaround; possible values:
0, 1, 2, 3
- read_to_read: Read-to-read turnaround; possible values:
0, 1, 2, 3
- write_to_write: Write-to-write turnaround; possible values:
0, 1, 2, 3
- active_powerdown_exit: Active powerdown exit timing; possible values:
1, 2, 3, 4, 5, 6, 7
- precharge_powerdown_exit: Precharge powerdown exit timing; possible values:
1, 2, 3, 4, 5, 6, 7
- odt_powerdown_exit: ODT powerdown exit timing; possible values:
0, 1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13, 14, 15
- mode_reg_set_cycle: Mode register set cycle time; possible values:
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
- precharge_to_activate: Precharge-to-acitvate interval; possible values:
1, 2, 3, 4, 5, 6, 7
- activate_to_precharge: Activate to precharge interval; possible values:
4, 5, 6, 7, 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, 18, 19
- activate_to_readwrite: Activate to read/write interval for SDRAM;
possible values:
1, 2, 3, 4, 5, 6, 7
- mcas_latency: MCAS latency from READ command; possible values:
* CASLAT_20
* CASLAT_25
* CASLAT_30
* CASLAT_35
* CASLAT_40
* CASLAT_45
* CASLAT_50
* CASLAT_55
* CASLAT_60
* CASLAT_65
* CASLAT_70
* CASLAT_75
* CASLAT_80
- refresh_recovery: Refresh recovery time; possible values:
8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23
- last_data_to_precharge: Last data to precharge minimum interval; possible
values:
1, 2, 3, 4, 5, 6, 7
- activate_to_activate: Activate-to-activate interval; possible values:
1, 2, 3, 4, 5, 6, 7
- last_write_data_to_read: Last write data pair to read command issue
interval; possible values:
1, 2, 3, 4, 5, 6, 7
- additive_latency: Additive latency; possible values:
0, 1, 2, 3, 4, 5
- mcas_to_preamble_override: MCAS-to-preamble-override; possible values:
* READ_LAT
* READ_LAT_PLUS_1_4
* READ_LAT_PLUS_1_2
* READ_LAT_PLUS_3_4
* READ_LAT_PLUS_1
* READ_LAT_PLUS_5_4
* READ_LAT_PLUS_3_2
* READ_LAT_PLUS_7_4
* READ_LAT_PLUS_2
* READ_LAT_PLUS_9_4
* READ_LAT_PLUS_5_2
* READ_LAT_PLUS_11_4
* READ_LAT_PLUS_3
* READ_LAT_PLUS_13_4
* READ_LAT_PLUS_7_2
* READ_LAT_PLUS_15_4
* READ_LAT_PLUS_4
* READ_LAT_PLUS_17_4
* READ_LAT_PLUS_9_2
* READ_LAT_PLUS_19_4
- write_latency: Write latency; possible values:
1, 2, 3, 4, 5, 6, 7
- read_to_precharge: Read to precharge; possible values:
1, 2, 3, 4
- write_cmd_to_write_data: Write command to write data strobe timing
adjustment; possible values:
* CLOCK_DELAY_0
* CLOCK_DELAY_1_4
* CLOCK_DELAY_1_2
* CLOCK_DELAY_3_4
* CLOCK_DELAY_1
* CLOCK_DELAY_5_4
* CLOCK_DELAY_3_2
- minimum_cke_pulse_width: Minimum CKE pulse width; possible values:
1, 2, 3, 4
- four_activates_window: Window for four activates; possible values:
1, 2, 3, 4 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, 18, 19
- self_refresh: Self refresh (during sleep); possible values:
* SREN_DISABLE
* SREN_ENABLE
- ecc: Support for ECC; possible values:
* ECC_DISABLE
* ECC_ENABLE
- registered_dram: Support for registered DRAM; possible values:
* RD_DISABLE
* RD_ENABLE
- sdram_type: Type of SDRAM device to be used; possible values:
* TYPE_DDR1
* TYPE_DDR2
- dynamic_power_management: Dynamic power management mode; possible values:
* DYN_PWR_DISABLE
* DYN_PWR_ENABLE
- databus_width: DRAM data bus width; possible values
* DATA_BUS_WIDTH_16
* DATA_BUS_WIDTH_32
- nc_auto_precharge: Non-concurrent auto-precharge; possible values:
* NCAP_DISABLE
* NCAP_ENABLE
- timing_2t: 2T timing; possible values:
* TIMING_1T
* TIMING_2T
- bank_interleaving_ctrl: Bank (chip select) interleaving control; possible
values:
* INTERLEAVE_NONE
* INTERLEAVE_1_AND_2
- precharge_bit_8: Precharge bin 8; possible values
* PRECHARGE_MA_10
* PRECHARGE_MA_8
- half_strength: Global half-strength override; possible values:
* STRENGTH_FULL
* STRENGTH_HALF
- bypass_initialization: Bypass initialization; possible values:
* INITIALIZATION_DONT_BYPASS
* INITIALIZATION_BYPASS
- force_self_refresh: Force self refresh; possible values:
* MODE_NORMAL
* MODE_REFRESH
- dll_reset: DLL reset; possible values:
* DLL_RESET_ENABLE
* DLL_RESET_DISABLE
- dqs_config: DQS configuration; possible values:
* DQS_TRUE
- odt_config: ODT configuration; possible values:
* ODT_ASSERT_NEVER
* ODT_ASSERT_WRITES
* ODT_ASSERT_READS
* ODT_ASSERT_ALWAYS
- posted_refreshes: Number of posted refreshes
1, 2, 3, 4, 5, 6, 7, 8
- sdmode: Initial value loaded into the DDR SDRAM mode
register
- esdmode: Initial value loaded into the DDR SDRAM extended
mode register
- esdmode2: Initial value loaded into the DDR SDRAM extended
mode 2 register
- esdmode3: Initial value loaded into the DDR SDRAM extended
mode 3 register
- refresh_interval: Refresh interval; possible values:
0 - 65535
- precharge_interval: Precharge interval; possible values:
0 - 16383
RAM module node:
================
Required properties:
- reg: A triple <cs addr size>, which consists of:
* cs - the chipselect used to drive this RAM module
* addr - the address where this RAM module's memory is map
to in the global memory space
* size - the size of the RAM module's memory in bytes
- auto_precharge: Chip select auto-precharge; possible values:
* AUTO_PRECHARGE_ENABLE
* AUTO_PRECHARGE_DISABLE
- odt_rd_cfg: ODT for reads configuration; possible values:
* ODT_RD_NEVER
* ODT_RD_ONLY_CURRENT
* ODT_RD_ONLY_OTHER_CS
* ODT_RD_ONLY_OTHER_DIMM
* ODT_RD_ALL
- odt_wr_cfg: ODT for writes configuration; possible values:
* ODT_WR_NEVER
* ODT_WR_ONLY_CURRENT
* ODT_WR_ONLY_OTHER_CS
* ODT_WR_ONLY_OTHER_DIMM
* ODT_WR_ALL
- bank_bits: Number of bank bits for SDRAM on chip select; possible
values:
2, 3
- row_bits: Number of row bits for SDRAM on chip select; possible values:
12, 13, 14
- col_bits: Number of column bits for SDRAM on chip select; possible
values:
8, 9, 10, 11
Example:
memory@2000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc83xx-mem-controller";
reg = <0x2000 0x1000>;
device_type = "memory";
u-boot,dm-pre-reloc;
driver_software_override = <DSO_ENABLE>;
p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
odt_termination_value = <ODT_TERMINATION_150_OHM>;
ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
clock_adjust = <CLOCK_ADJUST_05>;
read_to_write = <0>;
write_to_read = <0>;
read_to_read = <0>;
write_to_write = <0>;
active_powerdown_exit = <2>;
precharge_powerdown_exit = <6>;
odt_powerdown_exit = <8>;
mode_reg_set_cycle = <2>;
precharge_to_activate = <2>;
activate_to_precharge = <6>;
activate_to_readwrite = <2>;
mcas_latency = <CASLAT_40>;
refresh_recovery = <17>;
last_data_to_precharge = <2>;
activate_to_activate = <2>;
last_write_data_to_read = <2>;
additive_latency = <0>;
mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
write_latency = <3>;
read_to_precharge = <2>;
write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
minimum_cke_pulse_width = <3>;
four_activates_window = <5>;
self_refresh = <SREN_ENABLE>;
sdram_type = <TYPE_DDR2>;
databus_width = <DATA_BUS_WIDTH_32>;
force_self_refresh = <MODE_NORMAL>;
dll_reset = <DLL_RESET_ENABLE>;
dqs_config = <DQS_TRUE>;
odt_config = <ODT_ASSERT_READS>;
posted_refreshes = <1>;
refresh_interval = <2084>;
precharge_interval = <256>;
sdmode = <0x0242>;
esdmode = <0x0440>;
ram@0 {
reg = <0x0 0x0 0x8000000>;
compatible = "nanya,nt5tu64m16hg";
odt_rd_cfg = <ODT_RD_NEVER>;
odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
bank_bits = <3>;
row_bits = <13>;
col_bits = <10>;
};
};

2
MAINTAINERS
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@ -519,6 +519,8 @@ POWERPC MPC83XX
M: Mario Six <mario.six@gdsys.cc>
S: Maintained
T: git git://git.denx.de/u-boot-mpc83xx.git
F: drivers/ram/mpc83xx_sdram.c
F: include/dt-bindings/memory/mpc83xx-sdram.h
F: arch/powerpc/cpu/mpc83xx/
F: arch/powerpc/include/asm/arch-mpc83xx/

4
arch/powerpc/cpu/mpc83xx/spd_sdram.c
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@ -10,6 +10,8 @@
* Xianghua Xiao (X.Xiao@motorola.com)
*/
#ifndef CONFIG_MPC83XX_SDRAM
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
@ -924,3 +926,5 @@ void ddr_enable_ecc(unsigned int dram_size)
__asm__ __volatile__ ("isync");
}
#endif /* CONFIG_DDR_ECC */
#endif /* !CONFIG_MPC83XX_SDRAM */

9
drivers/ram/Kconfig
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@ -34,4 +34,13 @@ config STM32_SDRAM
support external memories like sdram, psram & nand.
This driver is for the sdram memory interface with the FMC.
config MPC83XX_SDRAM
bool "Enable MPC83XX SDRAM support"
depends on RAM
help
Enable support for the internal DDR Memory Controller of the MPC83xx
family of SoCs. Both static configurations, as well as configuring
the RAM through the use of SPD (Serial Presence Detect) is supported
via device tree settings.
source "drivers/ram/stm32mp1/Kconfig"

1
drivers/ram/Makefile
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@ -5,6 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_RAM) += ram-uclass.o
obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o
obj-$(CONFIG_SANDBOX) += sandbox_ram.o
obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/
obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o

1096
drivers/ram/mpc83xx_sdram.c Normal file
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File diff suppressed because it is too large Load Diff

161
include/dt-bindings/memory/mpc83xx-sdram.h Normal file
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@ -0,0 +1,161 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2018
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*/
#ifndef DT_BINDINGS_MPC83XX_SDRAM_H
#define DT_BINDINGS_MPC83XX_SDRAM_H
/* DDR Control Driver register */
#define DSO_DISABLE 0
#define DSO_ENABLE 1
#define DSO_P_IMPEDANCE_HIGHEST_Z 0x0
#define DSO_P_IMPEDANCE_MUCH_HIGHER_Z 0x8
#define DSO_P_IMPEDANCE_HIGHER_Z 0xC
#define DSO_P_IMPEDANCE_NOMINAL 0xE
#define DSO_P_IMPEDANCE_LOWER_Z 0xF
#define DSO_N_IMPEDANCE_HIGHEST_Z 0x0
#define DSO_N_IMPEDANCE_MUCH_HIGHER_Z 0x8
#define DSO_N_IMPEDANCE_HIGHER_Z 0xC
#define DSO_N_IMPEDANCE_NOMINAL 0xE
#define DSO_N_IMPEDANCE_LOWER_Z 0xF
#define ODT_TERMINATION_75_OHM 0
#define ODT_TERMINATION_150_OHM 1
#define DDR_TYPE_DDR2_1_8_VOLT 0
#define DDR_TYPE_DDR1_2_5_VOLT 1
#define MVREF_SEL_EXTERNAL 0
#define MVREF_SEL_INTERNAL_GVDD 1
#define M_ODR_ENABLE 0
#define M_ODR_DISABLE 1
/* CS config register */
#define AUTO_PRECHARGE_ENABLE 0x00800000
#define AUTO_PRECHARGE_DISABLE 0x00000000
#define ODT_RD_NEVER 0x00000000
#define ODT_RD_ONLY_CURRENT 0x00100000
#define ODT_RD_ONLY_OTHER_CS 0x00200000
#define ODT_RD_ONLY_OTHER_DIMM 0x00300000
#define ODT_RD_ALL 0x00400000
#define ODT_WR_NEVER 0x00000000
#define ODT_WR_ONLY_CURRENT 0x00010000
#define ODT_WR_ONLY_OTHER_CS 0x00020000
#define ODT_WR_ONLY_OTHER_DIMM 0x00030000
#define ODT_WR_ALL 0x00040000
/* DDR SDRAM Clock Control register */
#define CLOCK_ADJUST_025 0x01000000
#define CLOCK_ADJUST_05 0x02000000
#define CLOCK_ADJUST_075 0x03000000
#define CLOCK_ADJUST_1 0x04000000
#define CASLAT_20 0x3 /* CAS latency = 2.0 */
#define CASLAT_25 0x4 /* CAS latency = 2.5 */
#define CASLAT_30 0x5 /* CAS latency = 3.0 */
#define CASLAT_35 0x6 /* CAS latency = 3.5 */
#define CASLAT_40 0x7 /* CAS latency = 4.0 */
#define CASLAT_45 0x8 /* CAS latency = 4.5 */
#define CASLAT_50 0x9 /* CAS latency = 5.0 */
#define CASLAT_55 0xa /* CAS latency = 5.5 */
#define CASLAT_60 0xb /* CAS latency = 6.0 */
#define CASLAT_65 0xc /* CAS latency = 6.5 */
#define CASLAT_70 0xd /* CAS latency = 7.0 */
#define CASLAT_75 0xe /* CAS latency = 7.5 */
#define CASLAT_80 0xf /* CAS latency = 8.0 */
/* DDR SDRAM Timing Configuration 2 register */
#define READ_LAT_PLUS_1 0x0
#define READ_LAT 0x2
#define READ_LAT_PLUS_1_4 0x3
#define READ_LAT_PLUS_1_2 0x4
#define READ_LAT_PLUS_3_4 0x5
#define READ_LAT_PLUS_5_4 0x7
#define READ_LAT_PLUS_3_2 0x8
#define READ_LAT_PLUS_7_4 0x9
#define READ_LAT_PLUS_2 0xA
#define READ_LAT_PLUS_9_4 0xB
#define READ_LAT_PLUS_5_2 0xC
#define READ_LAT_PLUS_11_4 0xD
#define READ_LAT_PLUS_3 0xE
#define READ_LAT_PLUS_13_4 0xF
#define READ_LAT_PLUS_7_2 0x10
#define READ_LAT_PLUS_15_4 0x11
#define READ_LAT_PLUS_4 0x12
#define READ_LAT_PLUS_17_4 0x13
#define READ_LAT_PLUS_9_2 0x14
#define READ_LAT_PLUS_19_4 0x15
#define CLOCK_DELAY_0 0x0
#define CLOCK_DELAY_1_4 0x1
#define CLOCK_DELAY_1_2 0x2
#define CLOCK_DELAY_3_4 0x3
#define CLOCK_DELAY_1 0x4
#define CLOCK_DELAY_5_4 0x5
#define CLOCK_DELAY_3_2 0x6
/* DDR SDRAM Control Configuration */
#define SREN_DISABLE 0x0
#define SREN_ENABLE 0x1
#define ECC_DISABLE 0x0
#define ECC_ENABLE 0x1
#define RD_DISABLE 0x0
#define RD_ENABLE 0x1
#define TYPE_DDR1 0x2
#define TYPE_DDR2 0x3
#define DYN_PWR_DISABLE 0x0
#define DYN_PWR_ENABLE 0x1
#define DATA_BUS_WIDTH_16 0x1
#define DATA_BUS_WIDTH_32 0x2
#define NCAP_DISABLE 0x0
#define NCAP_ENABLE 0x1
#define TIMING_1T 0x0
#define TIMING_2T 0x1
#define INTERLEAVE_NONE 0x0
#define INTERLEAVE_1_AND_2 0x1
#define PRECHARGE_MA_10 0x0
#define PRECHARGE_MA_8 0x1
#define STRENGTH_FULL 0x0
#define STRENGTH_HALF 0x1
#define INITIALIZATION_DONT_BYPASS 0x0
#define INITIALIZATION_BYPASS 0x1
/* DDR SDRAM Control Configuration 2 register */
#define MODE_NORMAL 0x0
#define MODE_REFRESH 0x1
#define DLL_RESET_ENABLE 0x0
#define DLL_RESET_DISABLE 0x1
#define DQS_TRUE 0x0
#define ODT_ASSERT_NEVER 0x0
#define ODT_ASSERT_WRITES 0x1
#define ODT_ASSERT_READS 0x2
#define ODT_ASSERT_ALWAYS 0x3
#endif

6
include/mpc83xx.h
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@ -1110,6 +1110,8 @@
#define CSBNDS_EA 0x000000FF
#define CSBNDS_EA_SHIFT 24
#ifndef CONFIG_MPC83XX_SDRAM
/*
* CSn_CONFIG - Chip Select Configuration Register
*/
@ -1407,6 +1409,8 @@
#define ECC_ERROR_MAN_SBEC (0xff000000 >> 24)
#define ECC_ERROR_MAN_SBEC_SHIFT 0
#endif /* !CONFIG_MPC83XX_SDRAM */
/*
* CONFIG_ADDRESS - PCI Config Address Register
*/
@ -1510,6 +1514,7 @@
*/
#define PMCCR1_POWER_OFF 0x00000020
#ifndef CONFIG_RAM
/*
* DDRCDR - DDR Control Driver Register
*/
@ -1531,6 +1536,7 @@
#define DDRCDR_DDR_CFG 0x00040000
#define DDRCDR_M_ODR 0x00000002
#define DDRCDR_Q_DRN 0x00000001
#endif /* !CONFIG_RAM */
/*
* PCIE Bridge Register