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@@ -1,91 +0,0 @@
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/*
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* Copyright (C) 2008 Miromico AG
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*
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* Mostly copied form atmel ATNGW100 sources
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hmatrix.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mmu.h>
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#include <asm/arch/portmux.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
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{
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.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
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.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
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.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
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| MMU_VMR_CACHE_NONE,
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}, {
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.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
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.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
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.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
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| MMU_VMR_CACHE_WRBACK,
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},
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};
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static const struct sdram_config sdram_config = {
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.data_bits = SDRAM_DATA_32BIT,
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.row_bits = 13,
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.col_bits = 9,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 7,
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.trp = 2,
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.trcd = 2,
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.tras = 5,
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.txsr = 5,
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/* 7.81 us */
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.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
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};
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
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bis->bi_phy_id[0]);
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}
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#endif
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
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portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
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sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
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portmux_enable_usart1(PORTMUX_DRIVE_MIN);
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#if defined(CONFIG_MACB)
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portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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#endif
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#if defined(CONFIG_MMC)
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portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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gd->bd->bi_phy_id[0] = 0x01;
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return 0;
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}
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int board_postclk_init(void)
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{
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/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
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gclk_enable_output(3, PORTMUX_DRIVE_LOW);
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gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
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return 0;
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}
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Andreas Bießmann