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armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3

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Change tlb base address from OCRAM to DDR when exception level is
less than 3.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Pankit Garg 2018-11-05 18:01:28 +00:00 committed by York Sun
parent bb50569dc4
commit e350648046
1 changed files with 4 additions and 1 deletions
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5
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
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@ -371,7 +371,10 @@ static inline void early_mmu_setup(void)
unsigned int el = current_el();
/* global data is already setup, no allocation yet */
gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
if (el == 3)
gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
else
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
gd->arch.tlb_size = EARLY_PGTABLE_SIZE;