mpc8260: remove ep82xxm board support
This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
8eecbaf303
commit
e2b1962977
@ -16,9 +16,6 @@ config TARGET_CPU86
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config TARGET_CPU87
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bool "Support CPU87"
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config TARGET_EP82XXM
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bool "Support ep82xxm"
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config TARGET_KM82XX
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bool "Support km82xx"
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@ -27,7 +24,6 @@ endchoice
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source "board/atc/Kconfig"
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source "board/cpu86/Kconfig"
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source "board/cpu87/Kconfig"
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source "board/ep82xxm/Kconfig"
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source "board/keymile/km82xx/Kconfig"
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endmenu
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@ -1,9 +0,0 @@
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if TARGET_EP82XXM
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config SYS_BOARD
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default "ep82xxm"
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config SYS_CONFIG_NAME
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default "ep82xxm"
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endif
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@ -1,6 +0,0 @@
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EP82XXM BOARD
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#M: -
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S: Maintained
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F: board/ep82xxm/
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F: include/configs/ep82xxm.h
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F: configs/ep82xxm_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := ep82xxm.o
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@ -1,274 +0,0 @@
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/*
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* Copyright (C) 2006 Embedded Planet, LLC.
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*
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* Support for Embedded Planet EP82xxM boards.
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* Tested on EP82xxM (MPC8270).
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8260.h>
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#include <ioports.h>
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#include <asm/m8260_pci.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#endif
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#include <miiphy.h>
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#include <linux/compiler.h>
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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#define CONFIG_SYS_FCC2 1
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#define CONFIG_SYS_FCC3 1
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */
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/* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */
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/* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */
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/* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */
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/* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */
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/* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */
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/* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */
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/* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */
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/* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */
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/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
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/* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */
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/* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */
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/* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */
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/* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */
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/* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */
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/* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */
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/* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */
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/* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */
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/* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */
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/* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */
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/* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */
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/* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */
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/* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */
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/* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */
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/* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */
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/* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */
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/* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */
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/* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */
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/* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */
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},
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/* Port B */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
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/* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
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/* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */
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/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
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/* PC27 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */
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/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
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/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
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/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
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/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
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/* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */
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/* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */
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/* PC17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */
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/* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */
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/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */
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/* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */
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/* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */
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/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
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/* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */
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/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
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/* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */
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/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
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/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
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/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
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/* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */
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/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */
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/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
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/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
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/* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */
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/* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
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/* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */
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/* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */
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/* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */
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/* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */
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/* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */
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/* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */
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/* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */
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/* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */
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/* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */
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/* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */
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/* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
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}
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};
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#ifdef CONFIG_PCI
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typedef struct pci_ic_s {
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unsigned long pci_int_stat;
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unsigned long pci_int_mask;
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}pci_ic_t;
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#endif
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int board_early_init_f (void)
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{
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vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
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bcsr[4] |= 0x30; /* Turn the LEDs off */
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#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
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bcsr[6] |= 0x10;
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#endif
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#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
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bcsr[7] |= 0x10;
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#endif
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#if CONFIG_SYS_FCC3
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bcsr[8] |= 0xC0;
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#endif /* CONFIG_SYS_FCC3 */
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#if CONFIG_SYS_FCC2
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bcsr[8] |= 0x30;
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#endif /* CONFIG_SYS_FCC2 */
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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/* Size in MB of SDRAM populated on board*/
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long int msize = 256;
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#ifndef CONFIG_SYS_RAMBOOT
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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uint psdmr = CONFIG_SYS_PSDMR;
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int i;
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unsigned char *ramptr1 = (unsigned char *)0x00000110;
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__maybe_unused unsigned char ramtmp;
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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udelay(400);
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/* Initialise 60x bus SDRAM */
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memctl->memc_psrt = CONFIG_SYS_PSRT;
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memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
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memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
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memctl->memc_psdmr = psdmr;
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udelay(400);
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memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
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ramtmp = *ramptr1;
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memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
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for (i = 0; i < 8; i++) {
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memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
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}
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ramtmp = *ramptr1;
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memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
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*ramptr1 = 0xFF;
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memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
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#endif /* !CONFIG_SYS_RAMBOOT */
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/* Return total 60x bus SDRAM size */
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return msize * 1024 * 1024;
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}
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int checkboard(void)
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{
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vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
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puts("Board: ");
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switch (bcsr[0]) {
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case 0x0A:
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printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
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break;
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default:
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printf("unknown: ID=%02X\n", bcsr[0]);
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}
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return 0;
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}
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#ifdef CONFIG_PCI
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struct pci_controller hose;
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extern void pci_mpc8250_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc8250_init(&hose);
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}
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#endif
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@ -1,3 +0,0 @@
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CONFIG_PPC=y
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CONFIG_MPC8260=y
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CONFIG_TARGET_EP82XXM=y
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
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Board Arch CPU Commit Removed Last known maintainer/contact
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=================================================================================================
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ep82xxm powerpc mpc8260 - -
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gw8260 powerpc mpc8260 - - Oliver Brown <obrown@adventnetworks.com>
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IPHASE4539 powerpc mpc8260 - - Wolfgang Grandegger <wg@denx.de>
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muas3001 powerpc mpc8260 - - Heiko Schocher <hs@denx.de>
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@ -1,383 +0,0 @@
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/*
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* Copyright (C) 2006 Embedded Planet, LLC.
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*
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* U-Boot configuration for Embedded Planet EP82xxM boards.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CPU_ID_STR "MPC8270"
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#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
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/* 256MB SDRAM / 64MB FLASH */
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* Console is on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
|
||||
#undef CONFIG_CONS_NONE /* It's not on external UART */
|
||||
#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
|
||||
|
||||
#define CONFIG_SYS_BCSR 0xFA000000
|
||||
|
||||
/*
|
||||
* Select ethernet configuration
|
||||
*
|
||||
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
|
||||
* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
|
||||
* SCC, 1-3 for FCC)
|
||||
*
|
||||
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
|
||||
* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
|
||||
* must be unset.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */
|
||||
|
||||
|
||||
#define CONFIG_ETHER_ON_FCC2
|
||||
#define CONFIG_ETHER_ON_FCC3
|
||||
|
||||
#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
|
||||
#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
|
||||
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 0 /* Not used - implemented in BCSR */
|
||||
|
||||
#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
|
||||
#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
|
||||
#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
|
||||
|
||||
#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
|
||||
else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
|
||||
|
||||
#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
|
||||
else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
|
||||
#ifndef CONFIG_8260_CLKIN
|
||||
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ECHO
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DTT
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_DIAG
|
||||
|
||||
|
||||
#define CONFIG_ETHADDR 00:10:EC:00:88:65
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_ETH1ADDR 00:10:EC:80:88:65
|
||||
#define CONFIG_IPADDR 10.0.0.245
|
||||
#define CONFIG_HOSTNAME EP82xxM
|
||||
#define CONFIG_SERVERIP 10.0.0.26
|
||||
#define CONFIG_GATEWAYIP 10.0.0.1
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_ENV_IN_OWN_SECT 1
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3"
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
|
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
|
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
|
||||
#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "ep82xxm=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
/*
|
||||
* Define here the location of the environment variables (FLASH or EEPROM).
|
||||
* Note: DENX encourages to use redundant environment in FLASH.
|
||||
*/
|
||||
#if 1
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFC000000
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
/* EEPROM Configuration */
|
||||
#define CONFIG_SYS_EEPROM_SIZE 0x1000
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_EEPROM
|
||||
#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x0
|
||||
#endif /* CONFIG_ENV_IS_IN_EEPROM */
|
||||
|
||||
/* RTC Configuration */
|
||||
#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_M41T11_BASE_YEAR 1900
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM75 1
|
||||
#define CONFIG_DTT_SENSORS {0}
|
||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM Configuration
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
|
||||
#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_PCI_BOOTDELAY 0
|
||||
|
||||
/* PCI Memory map (if different from default map */
|
||||
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
|
||||
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
|
||||
#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
|
||||
PICMR_PREFETCH_EN)
|
||||
|
||||
/*
|
||||
* These are the windows that allow the CPU to access PCI address space.
|
||||
* All three PCI master windows, which allow the CPU to access PCI
|
||||
* prefetch, non prefetch, and IO space (see below), must all fit within
|
||||
* these windows.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Master window that allows the CPU to access PCI Memory (prefetch).
|
||||
* This window will be setup with the second set of Outbound ATU registers
|
||||
* in the bridge.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
|
||||
#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
|
||||
#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
|
||||
#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
|
||||
#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
|
||||
|
||||
/*
|
||||
* Master window that allows the CPU to access PCI Memory (non-prefetch).
|
||||
* This window will be setup with the second set of Outbound ATU registers
|
||||
* in the bridge.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
|
||||
#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
|
||||
#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
|
||||
#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
|
||||
#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
|
||||
|
||||
/*
|
||||
* Master window that allows the CPU to access PCI IO space.
|
||||
* This window will be setup with the first set of Outbound ATU registers
|
||||
* in the bridge.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
|
||||
#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
|
||||
#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
|
||||
#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
|
||||
#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
|
||||
|
||||
|
||||
/* PCIBR0 - for PCI IO*/
|
||||
#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
|
||||
#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
|
||||
/* PCIBR1 - prefetch and non-prefetch regions joined together */
|
||||
#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
|
||||
#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
|
||||
|
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
#if defined(CONFIG_CMD_JFFS2)
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
|
||||
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
|
||||
#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
|
||||
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
|
||||
#define CONFIG_SYS_JFFS_CUSTOM_PART
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_I2C)
|
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */
|
||||
|
||||
#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
|
||||
/* Hard reset configuration word */
|
||||
#define CONFIG_SYS_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */
|
||||
/* No slaves */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0
|
||||
#define CONFIG_SYS_HID0_FINAL 0
|
||||
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
#define CONFIG_SYS_SIUMCR 0x02610000
|
||||
#define CONFIG_SYS_SYPCR 0xFFFF0689
|
||||
#define CONFIG_SYS_BCR 0x8080E000
|
||||
#define CONFIG_SYS_SCCR 0x00000001
|
||||
|
||||
#define CONFIG_SYS_RMR 0
|
||||
#define CONFIG_SYS_TMCNTSC 0x000000C3
|
||||
#define CONFIG_SYS_PISCR 0x00000083
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x0A00
|
||||
#define CONFIG_SYS_PSDMR 0xC432246E
|
||||
#define CONFIG_SYS_PSRT 0x32
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
|
||||
#define CONFIG_SYS_SDRAM_OR 0xF0002900
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFC000882
|
||||
#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_BCSR | 0x00001001)
|
||||
#define CONFIG_SYS_OR4_PRELIM 0xFFF00050
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user