[MIPS] <asm/mipsregs.h>: Update coprocessor register access macros
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi
Shinya Kuribayashi
parent
1a3adac81c
commit
e2ad842662
@ -52,7 +52,7 @@ int checkboard (void)
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*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
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proc_id = read_32bit_cp0_register(CP0_PRID);
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proc_id = read_c0_prid();
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switch (proc_id >> 24) {
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case 0:
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@ -135,7 +135,7 @@ int checkboard (void)
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*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
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proc_id = read_32bit_cp0_register(CP0_PRID);
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proc_id = read_c0_prid();
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switch (proc_id >> 24) {
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case 0:
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@ -51,7 +51,7 @@ int checkboard (void)
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*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
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proc_id = read_32bit_cp0_register(CP0_PRID);
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proc_id = read_c0_prid();
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switch (proc_id >> 24) {
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case 0:
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@ -38,7 +38,7 @@ int checkboard(void)
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u32 proc_id;
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u32 config1;
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proc_id = read_32bit_cp0_register(CP0_PRID);
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proc_id = read_c0_prid();
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printf("Board: Qemu -M mips CPU: ");
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switch (proc_id) {
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case 0x00018000:
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@ -51,7 +51,7 @@ int checkboard(void)
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printf("4KEc");
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break;
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case 0x00019300:
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config1 = read_mips32_cp0_config1();
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config1 = read_c0_config1();
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if (config1 & 1)
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printf("24Kf");
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else
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@ -64,7 +64,7 @@ int checkboard(void)
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printf("R4000");
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break;
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case 0x00018100:
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config1 = read_mips32_cp0_config1();
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config1 = read_c0_config1();
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if (config1 & 1)
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printf("5Kf");
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else
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@ -66,10 +66,10 @@ void flush_cache(ulong start_addr, ulong size)
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
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{
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write_32bit_cp0_register(CP0_ENTRYLO0, low0);
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write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
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write_32bit_cp0_register(CP0_ENTRYLO1, low1);
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write_32bit_cp0_register(CP0_ENTRYHI, hi);
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write_32bit_cp0_register(CP0_INDEX, index);
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write_c0_entrylo0(low0);
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write_c0_pagemask(pagemask);
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write_c0_entrylo1(low1);
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write_c0_entryhi(hi);
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write_c0_index(index);
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tlb_write_indexed();
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}
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@ -207,81 +207,6 @@
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#define PL_64M 26
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#define PL_256M 28
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/*
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* Macros to access the system control coprocessor
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*/
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#define read_32bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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"mfc0\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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__res;})
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#define read_32bit_cp0_set1_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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"cfc0\t%0,"STR(source)"\n\t" \
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".set\tpop" \
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: "=r" (__res)); \
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__res;})
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/*
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* For now use this only with interrupts disabled!
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*/
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#define read_64bit_cp0_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmfc0\t%0,"STR(source)"\n\t" \
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".set\tmips0" \
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: "=r" (__res)); \
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__res;})
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#define write_32bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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"mtc0\t%0,"STR(register)"\n\t" \
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"nop" \
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: : "r" (value));
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#define write_32bit_cp0_set1_register(register,value) \
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__asm__ __volatile__( \
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"ctc0\t%0,"STR(register)"\n\t" \
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"nop" \
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: : "r" (value));
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#define write_64bit_cp0_register(register,value) \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmtc0\t%0,"STR(register)"\n\t" \
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".set\tmips0" \
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: : "r" (value))
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/*
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* This should be changed when we get a compiler that support the MIPS32 ISA.
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*/
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#define read_mips32_cp0_config1() \
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({ int __res; \
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__asm__ __volatile__( \
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".set\tnoreorder\n\t" \
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".set\tnoat\n\t" \
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".word\t0x40018001\n\t" \
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"move\t%0,$1\n\t" \
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".set\tat\n\t" \
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".set\treorder" \
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:"=r" (__res)); \
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__res;})
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#define tlb_write_indexed() \
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__asm__ __volatile__( \
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".set noreorder\n\t" \
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"tlbwi\n\t" \
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".set reorder")
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/*
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* R4x00 interrupt enable / cause bits
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*/
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@ -306,56 +231,6 @@
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#define C_IRQ4 (_ULCAST_(1) << 14)
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#define C_IRQ5 (_ULCAST_(1) << 15)
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#ifndef _LANGUAGE_ASSEMBLY
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/*
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* Manipulate the status register.
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* Mostly used to access the interrupt bits.
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*/
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#define __BUILD_SET_CP0(name,register) \
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extern __inline__ unsigned int \
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set_cp0_##name(unsigned int set) \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res |= set; \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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} \
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\
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extern __inline__ unsigned int \
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clear_cp0_##name(unsigned int clear) \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res &= ~clear; \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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} \
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\
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extern __inline__ unsigned int \
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change_cp0_##name(unsigned int change, unsigned int new) \
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{ \
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unsigned int res; \
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\
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res = read_32bit_cp0_register(register); \
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res &= ~change; \
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res |= (new & change); \
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if(change) \
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write_32bit_cp0_register(register, res); \
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\
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return res; \
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}
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__BUILD_SET_CP0(status,CP0_STATUS)
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__BUILD_SET_CP0(cause,CP0_CAUSE)
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__BUILD_SET_CP0(config,CP0_CONFIG)
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#endif /* defined (_LANGUAGE_ASSEMBLY) */
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/*
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* Bitfields in the R4xx0 cp0 status register
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*/
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@ -661,4 +536,829 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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#define MIPS_FPIR_L (_ULCAST_(1) << 21)
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#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
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#ifndef __ASSEMBLY__
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/*
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* Functions to access the R10000 performance counters. These are basically
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* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
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* performance counter number encoded into bits 1 ... 5 of the instruction.
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* Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
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* disassembler these will look like an access to sel 0 or 1.
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*/
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#define read_r10k_perf_cntr(counter) \
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({ \
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unsigned int __res; \
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__asm__ __volatile__( \
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"mfpc\t%0, %1" \
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: "=r" (__res) \
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: "i" (counter)); \
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\
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__res; \
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})
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#define write_r10k_perf_cntr(counter,val) \
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do { \
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__asm__ __volatile__( \
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"mtpc\t%0, %1" \
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: \
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: "r" (val), "i" (counter)); \
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} while (0)
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#define read_r10k_perf_event(counter) \
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({ \
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unsigned int __res; \
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__asm__ __volatile__( \
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"mfps\t%0, %1" \
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: "=r" (__res) \
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: "i" (counter)); \
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\
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__res; \
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})
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#define write_r10k_perf_cntl(counter,val) \
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do { \
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__asm__ __volatile__( \
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"mtps\t%0, %1" \
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: \
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: "r" (val), "i" (counter)); \
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} while (0)
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/*
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* Macros to access the system control coprocessor
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*/
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#define __read_32bit_c0_register(source, sel) \
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({ int __res; \
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if (sel == 0) \
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__asm__ __volatile__( \
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"mfc0\t%0, " #source "\n\t" \
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: "=r" (__res)); \
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else \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mfc0\t%0, " #source ", " #sel "\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__res)); \
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__res; \
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})
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#define __read_64bit_c0_register(source, sel) \
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({ unsigned long long __res; \
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if (sizeof(unsigned long) == 4) \
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__res = __read_64bit_c0_split(source, sel); \
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else if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmfc0\t%0, " #source "\n\t" \
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".set\tmips0" \
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: "=r" (__res)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmfc0\t%0, " #source ", " #sel "\n\t" \
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".set\tmips0" \
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: "=r" (__res)); \
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__res; \
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})
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#define __write_32bit_c0_register(register, sel, value) \
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do { \
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if (sel == 0) \
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__asm__ __volatile__( \
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"mtc0\t%z0, " #register "\n\t" \
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: : "Jr" ((unsigned int)(value))); \
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else \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mtc0\t%z0, " #register ", " #sel "\n\t" \
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".set\tmips0" \
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: : "Jr" ((unsigned int)(value))); \
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} while (0)
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#define __write_64bit_c0_register(register, sel, value) \
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do { \
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if (sizeof(unsigned long) == 4) \
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__write_64bit_c0_split(register, sel, value); \
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else if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips3\n\t" \
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"dmtc0\t%z0, " #register "\n\t" \
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".set\tmips0" \
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: : "Jr" (value)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmtc0\t%z0, " #register ", " #sel "\n\t" \
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".set\tmips0" \
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: : "Jr" (value)); \
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} while (0)
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#define __read_ulong_c0_register(reg, sel) \
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((sizeof(unsigned long) == 4) ? \
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(unsigned long) __read_32bit_c0_register(reg, sel) : \
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(unsigned long) __read_64bit_c0_register(reg, sel))
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#define __write_ulong_c0_register(reg, sel, val) \
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do { \
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if (sizeof(unsigned long) == 4) \
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__write_32bit_c0_register(reg, sel, val); \
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else \
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__write_64bit_c0_register(reg, sel, val); \
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} while (0)
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/*
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* On RM7000/RM9000 these are uses to access cop0 set 1 registers
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*/
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#define __read_32bit_c0_ctrl_register(source) \
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({ int __res; \
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__asm__ __volatile__( \
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"cfc0\t%0, " #source "\n\t" \
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: "=r" (__res)); \
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__res; \
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})
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#define __write_32bit_c0_ctrl_register(register, value) \
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do { \
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__asm__ __volatile__( \
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"ctc0\t%z0, " #register "\n\t" \
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: : "Jr" ((unsigned int)(value))); \
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} while (0)
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/*
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* These versions are only needed for systems with more than 38 bits of
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* physical address space running the 32-bit kernel. That's none atm :-)
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*/
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#define __read_64bit_c0_split(source, sel) \
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({ \
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unsigned long long __val; \
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unsigned long __flags; \
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\
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local_irq_save(__flags); \
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if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmfc0\t%M0, " #source "\n\t" \
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"dsll\t%L0, %M0, 32\n\t" \
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"dsrl\t%M0, %M0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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".set\tmips0" \
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: "=r" (__val)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dmfc0\t%M0, " #source ", " #sel "\n\t" \
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"dsll\t%L0, %M0, 32\n\t" \
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"dsrl\t%M0, %M0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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".set\tmips0" \
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: "=r" (__val)); \
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local_irq_restore(__flags); \
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\
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__val; \
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})
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#define __write_64bit_c0_split(source, sel, val) \
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do { \
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unsigned long __flags; \
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\
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local_irq_save(__flags); \
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if (sel == 0) \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dsll\t%L0, %L0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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"dsll\t%M0, %M0, 32\n\t" \
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"or\t%L0, %L0, %M0\n\t" \
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"dmtc0\t%L0, " #source "\n\t" \
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".set\tmips0" \
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: : "r" (val)); \
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else \
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__asm__ __volatile__( \
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".set\tmips64\n\t" \
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"dsll\t%L0, %L0, 32\n\t" \
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"dsrl\t%L0, %L0, 32\n\t" \
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"dsll\t%M0, %M0, 32\n\t" \
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"or\t%L0, %L0, %M0\n\t" \
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"dmtc0\t%L0, " #source ", " #sel "\n\t" \
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".set\tmips0" \
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: : "r" (val)); \
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local_irq_restore(__flags); \
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} while (0)
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#define read_c0_index() __read_32bit_c0_register($0, 0)
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#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
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#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
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#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
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#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
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#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
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#define read_c0_conf() __read_32bit_c0_register($3, 0)
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#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
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#define read_c0_context() __read_ulong_c0_register($4, 0)
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#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
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#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
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#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
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#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
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||||
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
|
||||
|
||||
#define read_c0_wired() __read_32bit_c0_register($6, 0)
|
||||
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
|
||||
|
||||
#define read_c0_info() __read_32bit_c0_register($7, 0)
|
||||
|
||||
#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
|
||||
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
|
||||
|
||||
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
|
||||
#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
|
||||
|
||||
#define read_c0_count() __read_32bit_c0_register($9, 0)
|
||||
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
|
||||
|
||||
#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
|
||||
#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
|
||||
|
||||
#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
|
||||
#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
|
||||
|
||||
#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
|
||||
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
|
||||
|
||||
#define read_c0_compare() __read_32bit_c0_register($11, 0)
|
||||
#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
|
||||
|
||||
#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
|
||||
#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
|
||||
|
||||
#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
|
||||
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
|
||||
|
||||
#define read_c0_status() __read_32bit_c0_register($12, 0)
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
#define write_c0_status(val) \
|
||||
do { \
|
||||
__write_32bit_c0_register($12, 0, val); \
|
||||
__ehb(); \
|
||||
} while (0)
|
||||
#else
|
||||
/*
|
||||
* Legacy non-SMTC code, which may be hazardous
|
||||
* but which might not support EHB
|
||||
*/
|
||||
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
|
||||
#define read_c0_cause() __read_32bit_c0_register($13, 0)
|
||||
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
|
||||
|
||||
#define read_c0_epc() __read_ulong_c0_register($14, 0)
|
||||
#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
|
||||
|
||||
#define read_c0_prid() __read_32bit_c0_register($15, 0)
|
||||
|
||||
#define read_c0_config() __read_32bit_c0_register($16, 0)
|
||||
#define read_c0_config1() __read_32bit_c0_register($16, 1)
|
||||
#define read_c0_config2() __read_32bit_c0_register($16, 2)
|
||||
#define read_c0_config3() __read_32bit_c0_register($16, 3)
|
||||
#define read_c0_config4() __read_32bit_c0_register($16, 4)
|
||||
#define read_c0_config5() __read_32bit_c0_register($16, 5)
|
||||
#define read_c0_config6() __read_32bit_c0_register($16, 6)
|
||||
#define read_c0_config7() __read_32bit_c0_register($16, 7)
|
||||
#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
|
||||
#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
|
||||
#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
|
||||
#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
|
||||
#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
|
||||
#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
|
||||
#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
|
||||
#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
|
||||
|
||||
/*
|
||||
* The WatchLo register. There may be upto 8 of them.
|
||||
*/
|
||||
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
|
||||
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
|
||||
#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
|
||||
#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
|
||||
#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
|
||||
#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
|
||||
#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
|
||||
#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
|
||||
#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
|
||||
#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
|
||||
#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
|
||||
#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
|
||||
#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
|
||||
#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
|
||||
#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
|
||||
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
|
||||
|
||||
/*
|
||||
* The WatchHi register. There may be upto 8 of them.
|
||||
*/
|
||||
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
|
||||
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
|
||||
#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
|
||||
#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
|
||||
#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
|
||||
#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
|
||||
#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
|
||||
#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
|
||||
|
||||
#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
|
||||
#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
|
||||
#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
|
||||
#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
|
||||
#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
|
||||
#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
|
||||
#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
|
||||
#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
|
||||
|
||||
#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
|
||||
#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
|
||||
|
||||
#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
|
||||
#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
|
||||
|
||||
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
|
||||
#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
|
||||
|
||||
/* RM9000 PerfControl performance counter control register */
|
||||
#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
|
||||
#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
|
||||
|
||||
#define read_c0_diag() __read_32bit_c0_register($22, 0)
|
||||
#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
|
||||
|
||||
#define read_c0_diag1() __read_32bit_c0_register($22, 1)
|
||||
#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
|
||||
|
||||
#define read_c0_diag2() __read_32bit_c0_register($22, 2)
|
||||
#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
|
||||
|
||||
#define read_c0_diag3() __read_32bit_c0_register($22, 3)
|
||||
#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
|
||||
|
||||
#define read_c0_diag4() __read_32bit_c0_register($22, 4)
|
||||
#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
|
||||
|
||||
#define read_c0_diag5() __read_32bit_c0_register($22, 5)
|
||||
#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
|
||||
|
||||
#define read_c0_debug() __read_32bit_c0_register($23, 0)
|
||||
#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
|
||||
|
||||
#define read_c0_depc() __read_ulong_c0_register($24, 0)
|
||||
#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
|
||||
|
||||
/*
|
||||
* MIPS32 / MIPS64 performance counters
|
||||
*/
|
||||
#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
|
||||
#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
|
||||
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
|
||||
#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
|
||||
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
|
||||
#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
|
||||
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
|
||||
#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
|
||||
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
|
||||
#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
|
||||
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
|
||||
#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
|
||||
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
|
||||
#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
|
||||
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
|
||||
#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
|
||||
|
||||
/* RM9000 PerfCount performance counter register */
|
||||
#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
|
||||
#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
|
||||
|
||||
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
|
||||
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
|
||||
|
||||
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
|
||||
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
|
||||
|
||||
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
|
||||
|
||||
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
|
||||
#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
|
||||
|
||||
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
|
||||
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
|
||||
|
||||
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
|
||||
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
|
||||
|
||||
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
|
||||
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
|
||||
|
||||
#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
|
||||
#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
|
||||
|
||||
/* MIPSR2 */
|
||||
#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
|
||||
#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
|
||||
|
||||
#define read_c0_intctl() __read_32bit_c0_register($12, 1)
|
||||
#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
|
||||
|
||||
#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
|
||||
#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
|
||||
|
||||
#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
|
||||
#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
|
||||
|
||||
#define read_c0_ebase() __read_32bit_c0_register($15, 1)
|
||||
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
|
||||
|
||||
/*
|
||||
* Macros to access the floating point coprocessor control registers
|
||||
*/
|
||||
#define read_32bit_cp1_register(source) \
|
||||
({ int __res; \
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
"cfc1\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
|
||||
#define rddsp(mask) \
|
||||
({ \
|
||||
unsigned int __res; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # rddsp $1, %x1 \n" \
|
||||
" .word 0x7c000cb8 | (%x1 << 16) \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__res) \
|
||||
: "i" (mask)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define wrdsp(val, mask) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # wrdsp $1, %x1 \n" \
|
||||
" .word 0x7c2004f8 | (%x1 << 11) \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (val), "i" (mask)); \
|
||||
} while (0)
|
||||
|
||||
#define mfhi0() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac0 \n" \
|
||||
" .word 0x00000810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi1() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac1 \n" \
|
||||
" .word 0x00200810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi2() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac2 \n" \
|
||||
" .word 0x00400810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi3() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac3 \n" \
|
||||
" .word 0x00600810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo0() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac0 \n" \
|
||||
" .word 0x00000812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo1() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac1 \n" \
|
||||
" .word 0x00200812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo2() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac2 \n" \
|
||||
" .word 0x00400812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo3() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac3 \n" \
|
||||
" .word 0x00600812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mthi0(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac0 \n" \
|
||||
" .word 0x00200011 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mthi1(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac1 \n" \
|
||||
" .word 0x00200811 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mthi2(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac2 \n" \
|
||||
" .word 0x00201011 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mthi3(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac3 \n" \
|
||||
" .word 0x00201811 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mtlo0(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac0 \n" \
|
||||
" .word 0x00200013 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mtlo1(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac1 \n" \
|
||||
" .word 0x00200813 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mtlo2(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac2 \n" \
|
||||
" .word 0x00201013 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mtlo3(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac3 \n" \
|
||||
" .word 0x00201813 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* TLB operations.
|
||||
*
|
||||
* It is responsibility of the caller to take care of any TLB hazards.
|
||||
*/
|
||||
static inline void tlb_probe(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbp\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
static inline void tlb_read(void)
|
||||
{
|
||||
#if MIPS34K_MISSED_ITLB_WAR
|
||||
int res = 0;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" .set noat \n"
|
||||
" .set mips32r2 \n"
|
||||
" .word 0x41610001 # dvpe $1 \n"
|
||||
" move %0, $1 \n"
|
||||
" ehb \n"
|
||||
" .set pop \n"
|
||||
: "=r" (res));
|
||||
|
||||
instruction_hazard();
|
||||
#endif
|
||||
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbr\n\t"
|
||||
".set reorder");
|
||||
|
||||
#if MIPS34K_MISSED_ITLB_WAR
|
||||
if ((res & _ULCAST_(1)))
|
||||
__asm__ __volatile__(
|
||||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" .set noat \n"
|
||||
" .set mips32r2 \n"
|
||||
" .word 0x41600021 # evpe \n"
|
||||
" ehb \n"
|
||||
" .set pop \n");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void tlb_write_indexed(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbwi\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
static inline void tlb_write_random(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set noreorder\n\t"
|
||||
"tlbwr\n\t"
|
||||
".set reorder");
|
||||
}
|
||||
|
||||
/*
|
||||
* Manipulate bits in a c0 register.
|
||||
*/
|
||||
#define __BUILD_SET_C0(name) \
|
||||
static inline unsigned int \
|
||||
set_c0_##name(unsigned int set) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res |= set; \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
} \
|
||||
\
|
||||
static inline unsigned int \
|
||||
clear_c0_##name(unsigned int clear) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res &= ~clear; \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
} \
|
||||
\
|
||||
static inline unsigned int \
|
||||
change_c0_##name(unsigned int change, unsigned int new) \
|
||||
{ \
|
||||
unsigned int res; \
|
||||
\
|
||||
res = read_c0_##name(); \
|
||||
res &= ~change; \
|
||||
res |= (new & change); \
|
||||
write_c0_##name(res); \
|
||||
\
|
||||
return res; \
|
||||
}
|
||||
|
||||
__BUILD_SET_C0(status)
|
||||
__BUILD_SET_C0(cause)
|
||||
__BUILD_SET_C0(config)
|
||||
__BUILD_SET_C0(intcontrol)
|
||||
__BUILD_SET_C0(intctl)
|
||||
__BUILD_SET_C0(srsmap)
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_MIPSREGS_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user