imx: mx6: correct enable_fec_anatop_clock
We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock, otherwise we may overridden configuration before enable_fec_anatop_clock. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
parent
1f8836396d
commit
e2748b4167
@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
|
||||
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
|
||||
return -EINVAL;
|
||||
|
||||
reg = readl(&anatop->pll_enet);
|
||||
|
||||
if (fec_id == 0) {
|
||||
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
|
||||
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
|
||||
|
Loading…
Reference in New Issue
Block a user