Merge branch 'master' of git://git.denx.de/u-boot-uniphier

arch/arm/Kconfig

@@ -793,6 +793,7 @@ config ARCH_UNIPHIER
 	bool "Panasonic UniPhier platform"
 	select CPU_V7
 	select SUPPORT_SPL
+	select OF_CONTROL if !SPL_BUILD
 
 endchoice
 

arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile

@@ -3,7 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
 								clkrst_init.o

arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c

@@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
 SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
 SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
 
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
 struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
 	{
 		.base = 0x5a800100,

arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile

@@ -3,7 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o

arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c

@@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
 SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
 SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
 
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
 struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
 	{
 		.base = 0x5a800100,

arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile

@@ -3,7 +3,7 @@
 #
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
-obj-y += platdevice.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
 								clkrst_init.o

arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c

@@ -14,7 +14,6 @@ SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
 SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
 SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
 
-/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
 struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
 	{
 		.base = 0x5a800100,

arch/arm/dts/Makefile

@@ -32,6 +32,10 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra114-dalmore.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-venice2.dtb
+dtb-$(CONFIG_ARCH_UNIPHIER) += \
+	uniphier-ph1-pro4-ref.dtb \
+	uniphier-ph1-ld4-ref.dtb \
+	uniphier-ph1-sld8-ref.dtb
 dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc706.dtb \
 	zynq-zed.dtb \

arch/arm/dts/uniphier-ph1-ld4-ref.dts

@@ -0,0 +1,42 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-ld4.dtsi"
+
+/ {
+	model = "Panasonic UniPhier PH1-LD4 Reference Board";
+	compatible = "panasonic,ph1-ld4-ref", "panasonic,ph1-ld4";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyPS0,115200 earlyprintk";
+		stdout-path = &uart0;
+	};
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&usb0 {
+      status = "okay";
+};
+
+&usb1 {
+      status = "okay";
+};

arch/arm/dts/uniphier-ph1-ld4.dtsi

@@ -0,0 +1,78 @@
+/*
+ * Device Tree Source for UniPhier PH1-LD4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "panasonic,ph1-ld4";
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		uart0: serial@54006800 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x20>;
+			clock-frequency = <36864000>;
+		};
+
+		uart1: serial@54006900 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x20>;
+			clock-frequency = <36864000>;
+		};
+
+		uart2: serial@54006a00 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x20>;
+			clock-frequency = <36864000>;
+		};
+
+		uart3: serial@54006b00 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x20>;
+			clock-frequency = <36864000>;
+		};
+
+		usb0: usb@5a800100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+		};
+
+		usb1: usb@5a810100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+		};
+
+		usb2: usb@5a820100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+		};
+	};
+};

arch/arm/dts/uniphier-ph1-pro4-ref.dts

@@ -0,0 +1,42 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+	model = "Panasonic UniPhier PH1-Pro4 Reference Board";
+	compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyPS0,115200 earlyprintk";
+		stdout-path = &uart0;
+	};
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&usb0 {
+      status = "okay";
+};
+
+&usb1 {
+      status = "okay";
+};

arch/arm/dts/uniphier-ph1-pro4.dtsi

@@ -0,0 +1,78 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "panasonic,ph1-pro4";
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		uart0: serial@54006800 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x20>;
+			clock-frequency = <73728000>;
+		};
+
+		uart1: serial@54006900 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x20>;
+			clock-frequency = <73728000>;
+		};
+
+		uart2: serial@54006a00 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x20>;
+			clock-frequency = <73728000>;
+		};
+
+		uart3: serial@54006b00 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x20>;
+			clock-frequency = <73728000>;
+		};
+
+		usb0: usb@5a800100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+		};
+
+		usb1: usb@5a810100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+		};
+	};
+};

arch/arm/dts/uniphier-ph1-sld8-ref.dts

@@ -0,0 +1,42 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld8.dtsi"
+
+/ {
+	model = "Panasonic UniPhier PH1-sLD8 Reference Board";
+	compatible = "panasonic,ph1-sld8-ref", "panasonic,ph1-sld8";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyPS0,115200 earlyprintk";
+		stdout-path = &uart0;
+	};
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&usb0 {
+      status = "okay";
+};
+
+&usb1 {
+      status = "okay";
+};

arch/arm/dts/uniphier-ph1-sld8.dtsi

@@ -0,0 +1,78 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD8 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "panasonic,ph1-sld8";
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		uart0: serial@54006800 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x20>;
+			clock-frequency = <80000000>;
+		};
+
+		uart1: serial@54006900 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x20>;
+			clock-frequency = <80000000>;
+		};
+
+		uart2: serial@54006a00 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x20>;
+			clock-frequency = <80000000>;
+		};
+
+		uart3: serial@54006b00 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006b00 0x20>;
+			clock-frequency = <80000000>;
+		};
+
+		usb0: usb@5a800100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+		};
+
+		usb1: usb@5a810100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+		};
+
+		usb2: usb@5a820100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+		};
+	};
+};

arch/arm/include/asm/arch-uniphier/gpio.h

@@ -0,0 +1,6 @@
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h even if GPIO is not supported.
+ */

configs/ph1_ld4_defconfig

@@ -1,7 +1,33 @@
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_LD4=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
 CONFIG_DM=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y

configs/ph1_pro4_defconfig

@@ -1,7 +1,33 @@
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_PRO4=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
 CONFIG_DM=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y

configs/ph1_sld8_defconfig

@@ -1,7 +1,33 @@
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_SLD8=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
 CONFIG_DM=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y

drivers/serial/serial_uniphier.c

@@ -11,6 +11,7 @@
 #include <dm/device.h>
 #include <dm/platform_data/serial-uniphier.h>
 #include <serial.h>
+#include <fdtdec.h>
 
 #define UART_REG(x)					\
 	u8 x;						\
@@ -113,19 +114,21 @@ static int uniphier_serial_remove(struct udevice *dev)
 }
 
 #ifdef CONFIG_OF_CONTROL
-static const struct udevice_id uniphier_uart_of_match = {
-	{ .compatible = "panasonic,uniphier-uart"},
+static const struct udevice_id uniphier_uart_of_match[] = {
+	{ .compatible = "panasonic,uniphier-uart" },
 	{},
 };
 
 static int uniphier_serial_ofdata_to_platdata(struct udevice *dev)
 {
-	/*
-	 * TODO: Masahiro Yamada (yamada.m@jp.panasonic.com)
-	 *
-	 * Implement conversion code from DTB to platform data
-	 * when supporting CONFIG_OF_CONTROL on UniPhir platform.
-	 */
+	struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
+	DECLARE_GLOBAL_DATA_PTR;
+
+	plat->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+	plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				       "clock-frequency", 0);
+
+	return 0;
 }
 #endif
 

drivers/usb/host/ehci-uniphier.c

@@ -6,10 +6,43 @@
  */
 
 #include <common.h>
+#include <linux/err.h>
 #include <usb.h>
 #include <asm/arch/ehci-uniphier.h>
 #include "ehci.h"
 
+#ifdef CONFIG_OF_CONTROL
+#include <fdtdec.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FDT		gd->fdt_blob
+#define COMPAT		"panasonic,uniphier-ehci"
+
+static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+{
+	int offset;
+
+	for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
+	     offset >= 0;
+	     offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
+		if (index == 0) {
+			*base = (struct ehci_hccr *)
+					fdtdec_get_addr(FDT, offset, "reg");
+			return 0;
+		}
+		index--;
+	}
+
+	return -ENODEV; /* not found */
+}
+#else
+static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
+{
+	*base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base;
+	return 0;
+}
+#endif
+
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
@@ -17,12 +50,15 @@
 int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
 		  struct ehci_hcor **hcor)
 {
+	int ret;
 	struct ehci_hccr *cr;
 	struct ehci_hcor *or;
 
 	uniphier_ehci_reset(index, 0);
 
-	cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base);
+	ret = get_uniphier_ehci_base(index, &cr);
+	if (ret < 0)
+		return ret;
 	or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
 
 	*hccr = cr;

include/configs/uniphier-common.h

@@ -112,7 +112,6 @@ are defined. Select only one of them."
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 
 #define CONFIG_CMDLINE_EDITING		/* add command line history	*/
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
@@ -143,15 +142,6 @@ are defined. Select only one of them."
  */
 #define CONFIG_ARP_TIMEOUT	500UL  /* 0.5 msec */
 
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_NAND		/* NAND flash suppport */
-
 #define CONFIG_SYS_MAX_NAND_DEVICE			1
 #define CONFIG_SYS_NAND_MAX_CHIPS			2
 #define CONFIG_SYS_NAND_ONFI_DETECTION
@@ -167,7 +157,6 @@ are defined. Select only one of them."
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS			0
 
 /* USB */
-#define CONFIG_CMD_USB
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		2
 #define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
@@ -225,10 +214,6 @@ are defined. Select only one of them."
 	"add_default_bootargs=setenv bootargs $bootargs"		\
 		" console=ttyS0,$baudrate\0"				\
 
-/* FIT support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
-
 /* Open Firmware flat tree */
 #define CONFIG_OF_LIBFDT