imx7ulp: synchronise device tree with linux
Synchronise device tree with linux v6.0-rc1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler
Stefano Babic
parent
af007620d2
commit
dfd0adc2f6
@ -32,6 +32,6 @@
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u-boot,dm-spl;
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};
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&gpio0 {
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&gpio_ptc {
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u-boot,dm-spl;
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};
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@ -1,12 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2019 NXP
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// Author: Fabio Estevam <fabio.estevam@nxp.com>
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/dts-v1/;
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#include "imx7ulp.dtsi"
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#include "imx7ulp-com-u-boot.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Embedded Artists i.MX7ULP COM";
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@ -16,9 +15,9 @@
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stdout-path = &lpuart4;
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};
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memory {
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x8000000>;
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reg = <0x60000000 0x4000000>;
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};
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};
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@ -37,11 +36,9 @@
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status = "okay";
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};
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&usbphy1 {
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fsl,tx-d-cal = <88>;
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};
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&usdhc0 {
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0>;
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non-removable;
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@ -51,15 +48,6 @@
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};
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&iomuxc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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IMX7ULP_PAD_PTC1__PTC1 0x20000
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>;
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};
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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@ -67,6 +55,12 @@
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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@ -82,10 +76,4 @@
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IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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>;
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};
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};
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@ -1,9 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Copyright 2017-2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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/dts-v1/;
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@ -12,365 +11,57 @@
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/ {
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model = "NXP i.MX7ULP EVK";
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compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
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compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
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stdout-path = &lpuart4;
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};
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bcmdhd_wlan_0: bcmdhd_wlan@0 {
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compatible = "android,bcmdhd_wlan";
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wlreg_on-supply = <&wlreg_on>;
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bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin";
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bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal";
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};
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memory {
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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backlight {
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compatible = "gpio-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_backlight>;
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gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
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default-on;
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compatible = "pwm-backlight";
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pwms = <&tpm4 1 50000 0>;
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brightness-levels = <0 20 25 30 35 40 100>;
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default-brightness-level = <6>;
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status = "okay";
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};
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mipi_dsi_reset: mipi-dsi-reset {
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compatible = "gpio-reset";
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reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
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reset-delay-us = <1000>;
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#reset-cells = <0>;
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reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_vbus>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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wlreg_on: fixedregulator@100 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-name = "wlreg_on";
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gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <100>;
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enable-active-high;
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};
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reg_usb_otg1_vbus: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_vbus>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_vsd_3v3: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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pf1550-rpmsg {
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compatible = "fsl,pf1550-rpmsg";
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sw1_reg: SW1 {
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regulator-name = "SW1";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1387500>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw2_reg: SW2 {
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regulator-name = "SW2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1387500>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3_reg: SW3 {
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regulator-name = "SW3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: VREFDDR {
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regulator-name = "VREFDDR";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vldo1_reg: LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vldo2_reg: LDO2 {
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regulator-name = "LDO2";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vldo3_reg: LDO3 {
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regulator-name = "LDO3";
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_vsd_3v3: regulator-vsd-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0_rst>;
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gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&iomuxc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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imx7ulp-evk {
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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IMX7ULP_PAD_PTC1__PTC1 0x20000
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>;
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};
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pinctrl_backlight: backlight_grp {
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fsl,pins = <
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IMX7ULP_PAD_PTF2__PTF2 0x20000
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>;
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};
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pinctrl_lpi2c5: lpi2c5grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27
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IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27
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>;
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};
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pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC19__PTC19 0x20003
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>;
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};
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
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>;
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};
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pinctrl_lpuart6: lpuart6grp {
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fsl,pins = <
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IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
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IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
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IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
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IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
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IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
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>;
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};
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pinctrl_lpuart7: lpuart7grp {
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fsl,pins = <
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IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
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IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
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IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
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IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */
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IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */
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>;
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};
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pinctrl_usdhc0_8bit: usdhc0grp_8bit {
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fsl,pins = <
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
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IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
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IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
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IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
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IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
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>;
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};
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pinctrl_lpi2c7: lpi2c7grp {
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fsl,pins = <
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IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27
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IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27
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>;
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};
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pinctrl_lpspi3: lpspi3grp {
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fsl,pins = <
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IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0
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IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0
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IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0
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IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0
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>;
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};
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pinctrl_usbotg1_vbus: otg1vbusgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC0__PTC0 0x20000
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43
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IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042
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IMX7ULP_PAD_PTE1__SDHC1_D0 0x43
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IMX7ULP_PAD_PTE0__SDHC1_D1 0x43
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IMX7ULP_PAD_PTE5__SDHC1_D2 0x43
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IMX7ULP_PAD_PTE4__SDHC1_D3 0x43
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>;
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};
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pinctrl_usdhc1_rst: usdhc1grp_rst {
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fsl,pins = <
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IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */
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IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */
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IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */
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IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */
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>;
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};
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pinctrl_dsi_hdmi: dsi_hdmi_grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */
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>;
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};
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};
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};
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&lcdif {
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status = "okay";
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disp-dev = "mipi_dsi_northwest";
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display = <&display0>;
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display0: display@0 {
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bits-per-pixel = <16>;
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bus-width = <24>;
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <9200000>;
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hactive = <480>;
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vactive = <272>;
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hfront-porch = <8>;
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hback-porch = <4>;
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hsync-len = <41>;
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vback-porch = <2>;
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vfront-porch = <4>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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};
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};
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&lpi2c7 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c7>;
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};
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&lpi2c5 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c5>;
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status = "okay";
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};
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&lpspi3 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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||||
pinctrl-0 = <&pinctrl_lpspi3>;
|
||||
status = "okay";
|
||||
|
||||
spidev0: spi@0 {
|
||||
reg = <0>;
|
||||
compatible = "rohm,dh2228fv";
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
|
||||
lcd_panel = "TRULY-WVGA-TFT3P5581E";
|
||||
resets = <&mipi_dsi_reset>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart4 { /* console */
|
||||
&lpuart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart6 { /* BT */
|
||||
&tpm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart7 { /* Uart test */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&rpmsg{
|
||||
pinctrl-0 = <&pinctrl_pwm0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -381,21 +72,62 @@
|
||||
srp-disable;
|
||||
hnp-disable;
|
||||
adp-disable;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy1 {
|
||||
fsl,tx-d-cal = <88>;
|
||||
};
|
||||
|
||||
&usdhc0 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc0>;
|
||||
pinctrl-1 = <&pinctrl_usdhc0>;
|
||||
pinctrl-2 = <&pinctrl_usdhc0>;
|
||||
pinctrl-3 = <&pinctrl_usdhc0>;
|
||||
cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
|
||||
cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_vsd_3v3>;
|
||||
vqmmc-supply = <&vldo2_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc1 {
|
||||
pinctrl_lpuart4: lpuart4grp {
|
||||
fsl,pins = <
|
||||
IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
|
||||
IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
|
||||
>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pinctrl_pwm0: pwm0grp {
|
||||
fsl,pins = <
|
||||
IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1_vbus: otg1vbusgrp {
|
||||
fsl,pins = <
|
||||
IMX7ULP_PAD_PTC0__PTC0 0x20000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1_id: otg1idgrp {
|
||||
fsl,pins = <
|
||||
IMX7ULP_PAD_PTC13__USB0_ID 0x10003
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc0: usdhc0grp {
|
||||
fsl,pins = <
|
||||
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
|
||||
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
|
||||
IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
|
||||
IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
|
||||
IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
|
||||
IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
|
||||
IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
|
||||
fsl,pins = <
|
||||
IMX7ULP_PAD_PTD0__PTD0 0x3
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,28 +1,29 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2018 NXP
|
||||
* Dong Aisheng <aisheng.dong@nxp.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx7ulp-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "imx7ulp-pinfunc.h"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio4;
|
||||
gpio1 = &gpio5;
|
||||
gpio2 = &gpio0;
|
||||
gpio3 = &gpio1;
|
||||
gpio4 = &gpio2;
|
||||
gpio5 = &gpio3;
|
||||
gpio0 = &gpio_ptc;
|
||||
gpio1 = &gpio_ptd;
|
||||
gpio2 = &gpio_pte;
|
||||
gpio3 = &gpio_ptf;
|
||||
i2c0 = &lpi2c6;
|
||||
i2c1 = &lpi2c7;
|
||||
mmc0 = &usdhc0;
|
||||
mmc1 = &usdhc1;
|
||||
serial0 = &lpuart4;
|
||||
@ -30,173 +31,95 @@
|
||||
serial2 = &lpuart6;
|
||||
serial3 = &lpuart7;
|
||||
usbphy0 = &usbphy1;
|
||||
usb0 = &usbotg1;
|
||||
i2c4 = &lpi2c4;
|
||||
i2c5 = &lpi2c5;
|
||||
i2c6 = &lpi2c6;
|
||||
i2c7 = &lpi2c7;
|
||||
spi0 = &qspi1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
cpu0: cpu@f00 {
|
||||
compatible = "arm,cortex-a7";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
reg = <0xf00>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* global autoconfigured region for contiguous allocations */
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0xC000000>;
|
||||
alignment = <0x2000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
|
||||
rpmsg_reserved: rpmsg@9FFF0000 {
|
||||
no-map;
|
||||
reg = <0x9FF00000 0x100000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
intc: interrupt-controller@40021000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x40021000 0x1000>,
|
||||
<0x40022000 0x100>;
|
||||
<0x40022000 0x1000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ckil: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "ckil";
|
||||
};
|
||||
|
||||
osc: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
sirc: clock@2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <16000000>;
|
||||
clock-output-names = "sirc";
|
||||
};
|
||||
|
||||
firc: clock@3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "firc";
|
||||
};
|
||||
|
||||
upll: clock@4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <480000000>;
|
||||
clock-output-names = "upll";
|
||||
};
|
||||
|
||||
mpll: clock@5 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <480000000>;
|
||||
clock-output-names = "mpll";
|
||||
};
|
||||
rosc: clock-rosc {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "rosc";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sram: sram@20000000 {
|
||||
compatible = "fsl,lpm-sram";
|
||||
reg = <0x1fffc000 0x4000>;
|
||||
sosc: clock-sosc {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "sosc";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ahbbridge0: ahb-bridge0@40000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
sirc: clock-sirc {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <16000000>;
|
||||
clock-output-names = "sirc";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
firc: clock-firc {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "firc";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
upll: clock-upll {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <480000000>;
|
||||
clock-output-names = "upll";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ahbbridge0: bus@40000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40000000 0x800000>;
|
||||
ranges;
|
||||
|
||||
edma0: dma-controller@40080000 {
|
||||
edma1: dma-controller@40080000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "nxp,imx7ulp-edma";
|
||||
compatible = "fsl,imx7ulp-edma";
|
||||
reg = <0x40080000 0x2000>,
|
||||
<0x40210000 0x1000>;
|
||||
dma-channels = <32>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dma", "dmamux0";
|
||||
clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
|
||||
};
|
||||
|
||||
mu: mu@40220000 {
|
||||
compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu";
|
||||
reg = <0x40220000 0x1000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
nmi: nmi@40220000 {
|
||||
compatible = "fsl,imx7ulp-nmi";
|
||||
reg = <0x40220000 0x1000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rpmsg: rpmsg{
|
||||
compatible = "fsl,imx7ulp-rpmsg";
|
||||
memory-region = <&rpmsg_reserved>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
snvs: snvs@40230000 {
|
||||
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
|
||||
reg = <0x40230000 0x10000>;
|
||||
|
||||
snvs_rtc: snvs-rtc-lp{
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
regmap =<&snvs>;
|
||||
offset = <0x34>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "snvs-rtc";
|
||||
clocks = <&clks IMX7ULP_CLK_SNVS>;
|
||||
};
|
||||
clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
|
||||
<&pcc2 IMX7ULP_CLK_DMA_MUX1>;
|
||||
};
|
||||
|
||||
crypto: crypto@40240000 {
|
||||
@ -205,8 +128,8 @@
|
||||
#size-cells = <1>;
|
||||
reg = <0x40240000 0x10000>;
|
||||
ranges = <0 0x40240000 0x10000>;
|
||||
clocks = <&clks IMX7ULP_CLK_CAAM>,
|
||||
<&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
|
||||
clock-names = "aclk", "ipg";
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
@ -222,105 +145,55 @@
|
||||
};
|
||||
};
|
||||
|
||||
tpm5: tpm@40260000 {
|
||||
compatible = "fsl,imx7ulp-tpm";
|
||||
reg = <0x40260000 0x1000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPTPM5>;
|
||||
};
|
||||
|
||||
lpit: 1@40270000 {
|
||||
compatible = "fsl,imx-lpit";
|
||||
reg = <0x40270000 0x1000>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
/* clocks = <&lpclk>;*/
|
||||
clocks = <&clks IMX7ULP_CLK_LPIT1>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
};
|
||||
|
||||
lpi2c4: lpi2c4@402B0000 {
|
||||
compatible = "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x402B0000 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPI2C4>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c5: lpi2c4@402C0000 {
|
||||
compatible = "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x402C0000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPI2C5>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi2: lpspi@40290000 {
|
||||
compatible = "fsl,imx7ulp-spi";
|
||||
reg = <0x40290000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPSPI2>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpspi3: lpspi@402A0000 {
|
||||
compatible = "fsl,imx7ulp-spi";
|
||||
reg = <0x402A0000 0x10000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPSPI3>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@402D0000 {
|
||||
lpuart4: serial@402d0000 {
|
||||
compatible = "fsl,imx7ulp-lpuart";
|
||||
reg = <0x402D0000 0x1000>;
|
||||
reg = <0x402d0000 0x1000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPUART4>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@402E0000 {
|
||||
lpuart5: serial@402e0000 {
|
||||
compatible = "fsl,imx7ulp-lpuart";
|
||||
reg = <0x402E0000 0x1000>;
|
||||
reg = <0x402e0000 0x1000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPUART5>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
dmas = <&edma0 0 20>, <&edma0 0 19>;
|
||||
dma-names = "tx","rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tpm4: pwm@40250000 {
|
||||
compatible = "fsl,imx7ulp-pwm";
|
||||
reg = <0x40250000 0x1000>;
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tpm5: tpm@40260000 {
|
||||
compatible = "fsl,imx7ulp-tpm";
|
||||
reg = <0x40260000 0x1000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_LPTPM5>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
usbotg1: usb@40330000 {
|
||||
compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb",
|
||||
"fsl,imx27-usb";
|
||||
compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
|
||||
reg = <0x40330000 0x200>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_USB0>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_USB0>;
|
||||
phys = <&usbphy1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
ahb-burst-config = <0x0>;
|
||||
tx-burst-size-dword = <0x8>;
|
||||
@ -329,314 +202,260 @@
|
||||
};
|
||||
|
||||
usbmisc1: usbmisc@40330200 {
|
||||
compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
|
||||
"fsl,imx6q-usbmisc";
|
||||
reg = <0x40330200 0x200>;
|
||||
};
|
||||
|
||||
usbphy1: usbphy@0x40350000 {
|
||||
compatible = "fsl,imx7ulp-usbphy",
|
||||
"fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
|
||||
usbphy1: usb-phy@40350000 {
|
||||
compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
|
||||
reg = <0x40350000 0x1000>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_USB_PHY>;
|
||||
nxp,sim = <&sim>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usdhc0: usdhc@40370000 {
|
||||
compatible = "fsl,imx7ulp-usdhc";
|
||||
usdhc0: mmc@40370000 {
|
||||
compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
|
||||
reg = <0x40370000 0x10000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&clks IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&clks IMX7ULP_CLK_USDHC0>;
|
||||
clock-names ="ipg", "ahb", "per";
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_USDHC0>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
fsl,tuning-step = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: usdhc@40380000 {
|
||||
compatible = "fsl,imx7ulp-usdhc";
|
||||
usdhc1: mmc@40380000 {
|
||||
compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
|
||||
reg = <0x40380000 0x10000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&clks IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&clks IMX7ULP_CLK_USDHC1>;
|
||||
clock-names ="ipg", "ahb", "per";
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_USDHC1>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
fsl,tuning-step = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@403D0000 {
|
||||
compatible = "fsl,imx7ulp-wdt";
|
||||
reg = <0x403D0000 0x10000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_WDG1>;
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
|
||||
assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
/*
|
||||
* As the 1KHz LPO clock rate is not trimed,the actually clock
|
||||
* is about 667Hz, so the init timeout 60s should set 40*1000
|
||||
* in the TOVAL register.
|
||||
*/
|
||||
timeout-sec = <40>;
|
||||
};
|
||||
|
||||
wdog2: wdog@40430000 {
|
||||
compatible = "fsl,imx7ulp-wdt";
|
||||
reg = <0x40430000 0x10000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_WDG2>;
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
|
||||
assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
timeout-sec = <40>;
|
||||
};
|
||||
|
||||
clks: scg1@403E0000 {
|
||||
scg1: clock-controller@403e0000 {
|
||||
compatible = "fsl,imx7ulp-scg1";
|
||||
reg = <0x403E0000 0x10000>;
|
||||
clocks = <&ckil>, <&osc>, <&sirc>,
|
||||
<&firc>, <&upll>, <&mpll>;
|
||||
clock-names = "ckil", "osc", "sirc",
|
||||
"firc", "upll", "mpll";
|
||||
reg = <0x403e0000 0x10000>;
|
||||
clocks = <&rosc>, <&sosc>, <&sirc>,
|
||||
<&firc>, <&upll>;
|
||||
clock-names = "rosc", "sosc", "sirc",
|
||||
"firc", "upll";
|
||||
#clock-cells = <1>;
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
|
||||
<&clks IMX7ULP_CLK_USDHC1>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
|
||||
<&clks IMX7ULP_CLK_NIC1_DIV>;
|
||||
};
|
||||
|
||||
pcc2: pcc2@403F0000 {
|
||||
compatible = "fsl,imx7ulp-pcc2";
|
||||
reg = <0x403F0000 0x10000>;
|
||||
wdog1: watchdog@403d0000 {
|
||||
compatible = "fsl,imx7ulp-wdt";
|
||||
reg = <0x403d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
|
||||
timeout-sec = <40>;
|
||||
};
|
||||
|
||||
pmc1: pmc1@40400000 {
|
||||
compatible = "fsl,imx7ulp-pmc1";
|
||||
reg = <0x40400000 0x1000>;
|
||||
pcc2: clock-controller@403f0000 {
|
||||
compatible = "fsl,imx7ulp-pcc2";
|
||||
reg = <0x403f0000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_DDR_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
|
||||
<&scg1 IMX7ULP_CLK_UPLL>,
|
||||
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_ROSC>,
|
||||
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
|
||||
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
|
||||
"apll_pfd2", "apll_pfd1", "apll_pfd0",
|
||||
"upll", "sosc_bus_clk",
|
||||
"firc_bus_clk", "rosc", "spll_bus_clk";
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
|
||||
};
|
||||
|
||||
smc1: smc1@40410000 {
|
||||
smc1: clock-controller@40410000 {
|
||||
compatible = "fsl,imx7ulp-smc1";
|
||||
reg = <0x40410000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
|
||||
clock-names = "divcore", "hsrun_divcore";
|
||||
};
|
||||
|
||||
pcc3: clock-controller@40b30000 {
|
||||
compatible = "fsl,imx7ulp-pcc3";
|
||||
reg = <0x40b30000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_DDR_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
|
||||
<&scg1 IMX7ULP_CLK_UPLL>,
|
||||
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_ROSC>,
|
||||
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
|
||||
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
|
||||
"apll_pfd2", "apll_pfd1", "apll_pfd0",
|
||||
"upll", "sosc_bus_clk",
|
||||
"firc_bus_clk", "rosc", "spll_bus_clk";
|
||||
};
|
||||
};
|
||||
|
||||
ahbbridge1: ahb-bridge1@40800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
ahbbridge1: bus@40800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40800000 0x800000>;
|
||||
ranges;
|
||||
|
||||
lpi2c6: lpi2c6@40A40000 {
|
||||
lpi2c6: i2c@40a40000 {
|
||||
compatible = "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x40A40000 0x10000>;
|
||||
reg = <0x40a40000 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPI2C6>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpi2c7: lpi2c7@40A50000 {
|
||||
lpi2c7: i2c@40a50000 {
|
||||
compatible = "fsl,imx7ulp-lpi2c";
|
||||
reg = <0x40A50000 0x10000>;
|
||||
reg = <0x40a50000 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPI2C7>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart6: serial@40A60000 {
|
||||
lpuart6: serial@40a60000 {
|
||||
compatible = "fsl,imx7ulp-lpuart";
|
||||
reg = <0x40A60000 0x1000>;
|
||||
reg = <0x40a60000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPUART6>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
dmas = <&edma0 0 22>, <&edma0 0 21>;
|
||||
dma-names = "tx","rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart7: serial@40A70000 {
|
||||
lpuart7: serial@40a70000 {
|
||||
compatible = "fsl,imx7ulp-lpuart";
|
||||
reg = <0x40A70000 0x1000>;
|
||||
reg = <0x40a70000 0x1000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPUART7>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
|
||||
clock-names = "ipg";
|
||||
assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
|
||||
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <50000000>;
|
||||
dmas = <&edma0 0 24>, <&edma0 0 23>;
|
||||
dma-names = "tx","rx";
|
||||
assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
|
||||
assigned-clock-rates = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lcdif: lcdif@40AA0000 {
|
||||
compatible = "fsl,imx7ulp-lcdif";
|
||||
reg = <0x40aa0000 0x10000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_DUMMY>,
|
||||
<&clks IMX7ULP_CLK_LCDIF>,
|
||||
<&clks IMX7ULP_CLK_DUMMY>;
|
||||
clock-names = "axi", "pix", "disp_axi";
|
||||
status = "disabled";
|
||||
memory-controller@40ab0000 {
|
||||
compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
|
||||
reg = <0x40ab0000 0x1000>;
|
||||
clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
|
||||
};
|
||||
|
||||
mipi_dsi: mipi_dsi@40A90000 {
|
||||
compatible = "fsl,imx7ulp-mipi-dsi";
|
||||
reg = <0x40A90000 0x10000>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_DSI>;
|
||||
clock-names = "mipi_dsi_clk";
|
||||
sim = <&sim>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmdc: mmdc@40ab0000 {
|
||||
compatible = "fsl,imx7ulp-mmdc";
|
||||
reg = <0x40ab0000 0x4000>;
|
||||
};
|
||||
|
||||
pcc3: pcc3@40B30000 {
|
||||
compatible = "fsl,imx7ulp-pcc3";
|
||||
reg = <0x40B30000 0x10000>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@4103D000 {
|
||||
compatible = "fsl,imx7ulp-iomuxc-0";
|
||||
reg = <0x4103D000 0x1000>;
|
||||
fsl,mux_mask = <0xf00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc1: iomuxc1@40ac0000 {
|
||||
compatible = "fsl,imx7ulp-iomuxc-1";
|
||||
iomuxc1: pinctrl@40ac0000 {
|
||||
compatible = "fsl,imx7ulp-iomuxc1";
|
||||
reg = <0x40ac0000 0x1000>;
|
||||
fsl,mux_mask = <0xf00>;
|
||||
};
|
||||
|
||||
gpio4: gpio@4103f000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x4103f000 0x1000 0x4100F000 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 0 32>;
|
||||
};
|
||||
|
||||
gpio5: gpio@41040000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x41040000 0x1000 0x4100F040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 32 32>;
|
||||
};
|
||||
|
||||
gpio0: gpio@40ae0000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
|
||||
gpio_ptc: gpio@40ae0000 {
|
||||
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
||||
reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc1 0 0 32>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLC>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 0 20>;
|
||||
};
|
||||
|
||||
gpio1: gpio@40af0000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x40af0000 0x1000 0x400F0040 0x40>;
|
||||
gpio_ptd: gpio@40af0000 {
|
||||
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
||||
reg = <0x40af0000 0x1000 0x400f0040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc1 0 32 32>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLD>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 32 12>;
|
||||
};
|
||||
|
||||
gpio2: gpio@40b00000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x40b00000 0x1000 0x400F0080 0x40>;
|
||||
gpio_pte: gpio@40b00000 {
|
||||
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
||||
reg = <0x40b00000 0x1000 0x400f0080 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc1 0 64 32>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLE>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 64 16>;
|
||||
};
|
||||
|
||||
gpio3: gpio@40b10000 {
|
||||
compatible = "fsl,imx7ulp-gpio";
|
||||
reg = <0x40b10000 0x1000 0x400F00c0 0x40>;
|
||||
gpio_ptf: gpio@40b10000 {
|
||||
compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
|
||||
reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc1 0 96 32>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
|
||||
<&pcc3 IMX7ULP_CLK_PCTLF>;
|
||||
clock-names = "gpio", "port";
|
||||
gpio-ranges = <&iomuxc1 0 96 20>;
|
||||
};
|
||||
};
|
||||
|
||||
pmc0: pmc0@410a1000 {
|
||||
compatible = "fsl,imx7ulp-pmc0";
|
||||
reg = <0x410a1000 0x1000>;
|
||||
};
|
||||
m4aips1: bus@41080000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x41080000 0x80000>;
|
||||
ranges;
|
||||
|
||||
sim: sim@410a3000 {
|
||||
compatible = "fsl,imx7ulp-sim", "syscon";
|
||||
reg = <0x410a3000 0x1000>;
|
||||
};
|
||||
|
||||
qspi1: qspi@410A5000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7ulp-qspi";
|
||||
reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_DUMMY>,
|
||||
<&clks IMX7ULP_CLK_DUMMY>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu: gpu@41800000 {
|
||||
compatible = "fsl,imx6q-gpu";
|
||||
reg = <0x41800000 0x80000>, <0x41880000 0x80000>,
|
||||
<0x60000000 0x40000000>, <0x0 0x4000000>;
|
||||
reg-names = "iobase_3d", "iobase_2d",
|
||||
"phys_baseaddr", "contiguous_mem";
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "irq_3d", "irq_2d";
|
||||
clocks = <&clks IMX7ULP_CLK_GPU3D>,
|
||||
<&clks IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&clks IMX7ULP_CLK_GPU_DIV>,
|
||||
<&clks IMX7ULP_CLK_GPU2D>,
|
||||
<&clks IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&clks IMX7ULP_CLK_NIC1_DIV>;
|
||||
clock-names = "gpu3d_clk", "gpu3d_shader_clk",
|
||||
"gpu3d_axi_clk", "gpu2d_clk",
|
||||
"gpu2d_shader_clk", "gpu2d_axi_clk";
|
||||
ocotp: efuse@410a6000 {
|
||||
compatible = "fsl,imx7ulp-ocotp", "syscon";
|
||||
reg = <0x410a6000 0x4000>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
|
||||
};
|
||||
};
|
||||
|
||||
imx_ion {
|
||||
compatible = "fsl,mxc-ion";
|
||||
fsl,heap-id = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,21 +1,19 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
* Copyright 2017~2018 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX7ULP_H
|
||||
|
||||
#define IMX7ULP_CLK_DUMMY 0
|
||||
#define IMX7ULP_CLK_CKIL 1
|
||||
#define IMX7ULP_CLK_OSC 2
|
||||
#define IMX7ULP_CLK_FIRC 3
|
||||
|
||||
/* SCG1 */
|
||||
|
||||
#define IMX7ULP_CLK_DUMMY 0
|
||||
#define IMX7ULP_CLK_ROSC 1
|
||||
#define IMX7ULP_CLK_SOSC 2
|
||||
#define IMX7ULP_CLK_FIRC 3
|
||||
#define IMX7ULP_CLK_SPLL_PRE_SEL 4
|
||||
#define IMX7ULP_CLK_SPLL_PRE_DIV 5
|
||||
#define IMX7ULP_CLK_SPLL 6
|
||||
@ -51,111 +49,71 @@
|
||||
#define IMX7ULP_CLK_NIC1_DIV 36
|
||||
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
|
||||
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
|
||||
/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
|
||||
#define IMX7ULP_CLK_MIPI_PLL 39
|
||||
#define IMX7ULP_CLK_SIRC 40
|
||||
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
|
||||
#define IMX7ULP_CLK_FIRC_BUS_CLK 42
|
||||
#define IMX7ULP_CLK_SPLL_BUS_CLK 43
|
||||
#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
|
||||
#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
|
||||
|
||||
/* PCG2 */
|
||||
#define IMX7ULP_CLK_DMA1 39
|
||||
#define IMX7ULP_CLK_RGPIO2P1 40
|
||||
#define IMX7ULP_CLK_FLEXBUS 41
|
||||
#define IMX7ULP_CLK_SEMA42_1 42
|
||||
#define IMX7ULP_CLK_DMA_MUX1 43
|
||||
#define IMX7ULP_CLK_SNVS 44
|
||||
#define IMX7ULP_CLK_CAAM 45
|
||||
#define IMX7ULP_CLK_LPTPM4 46
|
||||
#define IMX7ULP_CLK_LPTPM5 47
|
||||
#define IMX7ULP_CLK_LPIT1 48
|
||||
#define IMX7ULP_CLK_LPSPI2 49
|
||||
#define IMX7ULP_CLK_LPSPI3 50
|
||||
#define IMX7ULP_CLK_LPI2C4 51
|
||||
#define IMX7ULP_CLK_LPI2C5 52
|
||||
#define IMX7ULP_CLK_LPUART4 53
|
||||
#define IMX7ULP_CLK_LPUART5 54
|
||||
#define IMX7ULP_CLK_FLEXIO1 55
|
||||
#define IMX7ULP_CLK_USB0 56
|
||||
#define IMX7ULP_CLK_USB1 57
|
||||
#define IMX7ULP_CLK_USB_PHY 58
|
||||
#define IMX7ULP_CLK_USB_PL301 59
|
||||
#define IMX7ULP_CLK_USDHC0 60
|
||||
#define IMX7ULP_CLK_USDHC1 61
|
||||
#define IMX7ULP_CLK_WDG1 62
|
||||
#define IMX7ULP_CLK_WDG2 63
|
||||
#define IMX7ULP_CLK_CORE 46
|
||||
#define IMX7ULP_CLK_HSRUN_CORE 47
|
||||
|
||||
/* PCG3 */
|
||||
#define IMX7ULP_CLK_LPTPM6 64
|
||||
#define IMX7ULP_CLK_LPTPM7 65
|
||||
#define IMX7ULP_CLK_LPI2C6 66
|
||||
#define IMX7ULP_CLK_LPI2C7 67
|
||||
#define IMX7ULP_CLK_LPUART6 68
|
||||
#define IMX7ULP_CLK_LPUART7 69
|
||||
#define IMX7ULP_CLK_VIU 70
|
||||
#define IMX7ULP_CLK_DSI 71
|
||||
#define IMX7ULP_CLK_LCDIF 72
|
||||
#define IMX7ULP_CLK_MMDC 73
|
||||
#define IMX7ULP_CLK_PCTLC 74
|
||||
#define IMX7ULP_CLK_PCTLD 75
|
||||
#define IMX7ULP_CLK_PCTLE 76
|
||||
#define IMX7ULP_CLK_PCTLF 77
|
||||
#define IMX7ULP_CLK_GPU3D 78
|
||||
#define IMX7ULP_CLK_GPU2D 79
|
||||
#define IMX7ULP_CLK_SCG1_END 48
|
||||
|
||||
#define IMX7ULP_CLK_MIPI_PLL 80
|
||||
#define IMX7ULP_CLK_SIRC 81
|
||||
/* PCC2 */
|
||||
#define IMX7ULP_CLK_DMA1 0
|
||||
#define IMX7ULP_CLK_RGPIO2P1 1
|
||||
#define IMX7ULP_CLK_FLEXBUS 2
|
||||
#define IMX7ULP_CLK_SEMA42_1 3
|
||||
#define IMX7ULP_CLK_DMA_MUX1 4
|
||||
#define IMX7ULP_CLK_CAAM 6
|
||||
#define IMX7ULP_CLK_LPTPM4 7
|
||||
#define IMX7ULP_CLK_LPTPM5 8
|
||||
#define IMX7ULP_CLK_LPIT1 9
|
||||
#define IMX7ULP_CLK_LPSPI2 10
|
||||
#define IMX7ULP_CLK_LPSPI3 11
|
||||
#define IMX7ULP_CLK_LPI2C4 12
|
||||
#define IMX7ULP_CLK_LPI2C5 13
|
||||
#define IMX7ULP_CLK_LPUART4 14
|
||||
#define IMX7ULP_CLK_LPUART5 15
|
||||
#define IMX7ULP_CLK_FLEXIO1 16
|
||||
#define IMX7ULP_CLK_USB0 17
|
||||
#define IMX7ULP_CLK_USB1 18
|
||||
#define IMX7ULP_CLK_USB_PHY 19
|
||||
#define IMX7ULP_CLK_USB_PL301 20
|
||||
#define IMX7ULP_CLK_USDHC0 21
|
||||
#define IMX7ULP_CLK_USDHC1 22
|
||||
#define IMX7ULP_CLK_WDG1 23
|
||||
#define IMX7ULP_CLK_WDG2 24
|
||||
|
||||
#define IMX7ULP_CLK_SCG1_CLKOUT 82
|
||||
#define IMX7ULP_CLK_PCC2_END 25
|
||||
|
||||
#define IMX7ULP_CLK_END 83
|
||||
/* PCC3 */
|
||||
#define IMX7ULP_CLK_LPTPM6 0
|
||||
#define IMX7ULP_CLK_LPTPM7 1
|
||||
#define IMX7ULP_CLK_LPI2C6 2
|
||||
#define IMX7ULP_CLK_LPI2C7 3
|
||||
#define IMX7ULP_CLK_LPUART6 4
|
||||
#define IMX7ULP_CLK_LPUART7 5
|
||||
#define IMX7ULP_CLK_VIU 6
|
||||
#define IMX7ULP_CLK_DSI 7
|
||||
#define IMX7ULP_CLK_LCDIF 8
|
||||
#define IMX7ULP_CLK_MMDC 9
|
||||
#define IMX7ULP_CLK_PCTLC 10
|
||||
#define IMX7ULP_CLK_PCTLD 11
|
||||
#define IMX7ULP_CLK_PCTLE 12
|
||||
#define IMX7ULP_CLK_PCTLF 13
|
||||
#define IMX7ULP_CLK_GPU3D 14
|
||||
#define IMX7ULP_CLK_GPU2D 15
|
||||
|
||||
/*cm4 clocks*/
|
||||
#define IMX7ULP_CM4_CLK_DUMMY 0
|
||||
#define IMX7ULP_CM4_CLK_CKIL 1
|
||||
#define IMX7ULP_CM4_CLK_OSC 2
|
||||
#define IMX7ULP_CM4_CLK_FIRC 3
|
||||
#define IMX7ULP_CM4_CLK_SIRC 4
|
||||
#define IMX7ULP_CLK_PCC3_END 16
|
||||
|
||||
/* SCG0 */
|
||||
#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5
|
||||
#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6
|
||||
#define IMX7ULP_CM4_CLK_SPLL 7
|
||||
#define IMX7ULP_CM4_CLK_SPLL_VCO 8
|
||||
#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9
|
||||
#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10
|
||||
#define IMX7ULP_CM4_CLK_SPLL_PFD0 11
|
||||
#define IMX7ULP_CM4_CLK_SPLL_PFD1 12
|
||||
#define IMX7ULP_CM4_CLK_SPLL_PFD2 13
|
||||
#define IMX7ULP_CM4_CLK_SPLL_PFD3 14
|
||||
#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15
|
||||
#define IMX7ULP_CM4_CLK_SPLL_PFD 16
|
||||
#define IMX7ULP_CM4_CLK_SPLL_SEL 17
|
||||
#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18
|
||||
#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19
|
||||
#define IMX7ULP_CM4_CLK_APLL 20
|
||||
#define IMX7ULP_CM4_CLK_APLL_VCO 21
|
||||
#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22
|
||||
#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23
|
||||
#define IMX7ULP_CM4_CLK_APLL_PFD0 24
|
||||
#define IMX7ULP_CM4_CLK_APLL_PFD1 25
|
||||
#define IMX7ULP_CM4_CLK_APLL_PFD2 26
|
||||
#define IMX7ULP_CM4_CLK_APLL_PFD3 27
|
||||
#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28
|
||||
#define IMX7ULP_CM4_CLK_APLL_PFD 29
|
||||
#define IMX7ULP_CM4_CLK_APLL_SEL 30
|
||||
#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31
|
||||
#define IMX7ULP_CM4_CLK_SYS_SEL 32
|
||||
#define IMX7ULP_CM4_CLK_CORE_DIV 33
|
||||
#define IMX7ULP_CM4_CLK_BUS_DIV 34
|
||||
#define IMX7ULP_CM4_CLK_PLAT_DIV 35
|
||||
#define IMX7ULP_CM4_CLK_SLOW_DIV 36
|
||||
/* SMC1 */
|
||||
#define IMX7ULP_CLK_ARM 0
|
||||
|
||||
#define IMX7ULP_CM4_CLK_SAI0_SEL 37
|
||||
#define IMX7ULP_CM4_CLK_SAI0_DIV 38
|
||||
#define IMX7ULP_CM4_CLK_SAI0_ROOT 39
|
||||
#define IMX7ULP_CM4_CLK_SAI0_IPG 40
|
||||
#define IMX7ULP_CM4_CLK_SAI1_SEL 41
|
||||
#define IMX7ULP_CM4_CLK_SAI1_DIV 42
|
||||
#define IMX7ULP_CM4_CLK_SAI1_ROOT 43
|
||||
#define IMX7ULP_CM4_CLK_SAI1_IPG 44
|
||||
|
||||
#define IMX7ULP_CLK_SCG0_CLKOUT 45
|
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#define IMX7ULP_CM4_CLK_END 46
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#define IMX7ULP_CLK_SMC1_END 1
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#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
|
||||
|
||||
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Reference in New Issue
Block a user