stm32mp: fdt: update etzpc for STM32MP13x
Add support of STM32MP13x the ETZPC part of fdt.c Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Change-Id: If2777fbf66b8525a2a447056780aaa04e6b0a9a0
This commit is contained in:
Patrick Delaunay
parent
ca9c9e7e92
commit
df68a30979
@ -28,12 +28,119 @@
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#define ETZPC_RESERVED 0xffffffff
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#define STM32MP13_FDCAN_BASE 0x4400F000
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#define STM32MP13_ADC1_BASE 0x48003000
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#define STM32MP13_TSC_BASE 0x5000B000
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#define STM32MP13_CRYP_BASE 0x54002000
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#define STM32MP13_ETH2_BASE 0x5800E000
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#define STM32MP13_DCMIPP_BASE 0x5A000000
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#define STM32MP13_LTDC_BASE 0x5A010000
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#define STM32MP15_FDCAN_BASE 0x4400e000
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#define STM32MP15_CRYP2_BASE 0x4c005000
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#define STM32MP15_CRYP1_BASE 0x54001000
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#define STM32MP15_GPU_BASE 0x59000000
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#define STM32MP15_DSI_BASE 0x5a000000
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static const u32 stm32mp13_ip_addr[] = {
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0x50025000, /* 0 VREFBUF APB3 */
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0x50021000, /* 1 LPTIM2 APB3 */
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0x50022000, /* 2 LPTIM3 APB3 */
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STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */
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STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
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0x5A006000, /* 5 USBPHYCTRL APB4 */
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0x5A003000, /* 6 DDRCTRLPHY APB4 */
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ETZPC_RESERVED, /* 7 Reserved*/
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ETZPC_RESERVED, /* 8 Reserved*/
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ETZPC_RESERVED, /* 9 Reserved*/
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0x5C006000, /* 10 TZC APB5 */
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0x58001000, /* 11 MCE APB5 */
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0x5C000000, /* 12 IWDG1 APB5 */
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0x5C008000, /* 13 STGENC APB5 */
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ETZPC_RESERVED, /* 14 Reserved*/
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ETZPC_RESERVED, /* 15 Reserved*/
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0x4C000000, /* 16 USART1 APB6 */
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0x4C001000, /* 17 USART2 APB6 */
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0x4C002000, /* 18 SPI4 APB6 */
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0x4C003000, /* 19 SPI5 APB6 */
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0x4C004000, /* 20 I2C3 APB6 */
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0x4C005000, /* 21 I2C4 APB6 */
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0x4C006000, /* 22 I2C5 APB6 */
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0x4C007000, /* 23 TIM12 APB6 */
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0x4C008000, /* 24 TIM13 APB6 */
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0x4C009000, /* 25 TIM14 APB6 */
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0x4C00A000, /* 26 TIM15 APB6 */
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0x4C00B000, /* 27 TIM16 APB6 */
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0x4C00C000, /* 28 TIM17 APB6 */
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ETZPC_RESERVED, /* 29 Reserved*/
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ETZPC_RESERVED, /* 30 Reserved*/
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ETZPC_RESERVED, /* 31 Reserved*/
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STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */
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0x48004000, /* 33 ADC2 AHB2 */
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0x49000000, /* 34 OTG AHB2 */
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ETZPC_RESERVED, /* 35 Reserved*/
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ETZPC_RESERVED, /* 36 Reserved*/
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STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
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ETZPC_RESERVED, /* 38 Reserved*/
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ETZPC_RESERVED, /* 39 Reserved*/
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0x54004000, /* 40 RNG AHB5 */
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0x54003000, /* 41 HASH AHB5 */
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STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */
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0x54005000, /* 43 SAES AHB5 */
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0x54006000, /* 44 PKA AHB5 */
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0x54000000, /* 45 BKPSRAM AHB5 */
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ETZPC_RESERVED, /* 46 Reserved*/
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ETZPC_RESERVED, /* 47 Reserved*/
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0x5800A000, /* 48 ETH1 AHB6 */
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STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */
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0x58005000, /* 50 SDMMC1 AHB6 */
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0x58007000, /* 51 SDMMC2 AHB6 */
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ETZPC_RESERVED, /* 52 Reserved*/
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ETZPC_RESERVED, /* 53 Reserved*/
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0x58002000, /* 54 FMC AHB6 */
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0x58003000, /* 55 QSPI AHB6 */
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ETZPC_RESERVED, /* 56 Reserved*/
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ETZPC_RESERVED, /* 57 Reserved*/
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ETZPC_RESERVED, /* 58 Reserved*/
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ETZPC_RESERVED, /* 59 Reserved*/
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0x30000000, /* 60 SRAM1 MLAHB */
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0x30004000, /* 61 SRAM2 MLAHB */
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0x30006000, /* 62 SRAM3 MLAHB */
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ETZPC_RESERVED, /* 63 Reserved*/
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ETZPC_RESERVED, /* 64 Reserved*/
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ETZPC_RESERVED, /* 65 Reserved*/
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ETZPC_RESERVED, /* 66 Reserved*/
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ETZPC_RESERVED, /* 67 Reserved*/
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ETZPC_RESERVED, /* 68 Reserved*/
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ETZPC_RESERVED, /* 69 Reserved*/
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ETZPC_RESERVED, /* 70 Reserved*/
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ETZPC_RESERVED, /* 71 Reserved*/
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ETZPC_RESERVED, /* 72 Reserved*/
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ETZPC_RESERVED, /* 73 Reserved*/
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ETZPC_RESERVED, /* 74 Reserved*/
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ETZPC_RESERVED, /* 75 Reserved*/
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ETZPC_RESERVED, /* 76 Reserved*/
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ETZPC_RESERVED, /* 77 Reserved*/
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ETZPC_RESERVED, /* 78 Reserved*/
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ETZPC_RESERVED, /* 79 Reserved*/
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ETZPC_RESERVED, /* 80 Reserved*/
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ETZPC_RESERVED, /* 81 Reserved*/
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ETZPC_RESERVED, /* 82 Reserved*/
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ETZPC_RESERVED, /* 83 Reserved*/
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ETZPC_RESERVED, /* 84 Reserved*/
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ETZPC_RESERVED, /* 85 Reserved*/
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ETZPC_RESERVED, /* 86 Reserved*/
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ETZPC_RESERVED, /* 87 Reserved*/
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ETZPC_RESERVED, /* 88 Reserved*/
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ETZPC_RESERVED, /* 89 Reserved*/
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ETZPC_RESERVED, /* 90 Reserved*/
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ETZPC_RESERVED, /* 91 Reserved*/
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ETZPC_RESERVED, /* 92 Reserved*/
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ETZPC_RESERVED, /* 93 Reserved*/
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ETZPC_RESERVED, /* 94 Reserved*/
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ETZPC_RESERVED, /* 95 Reserved*/
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};
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static const u32 stm32mp15_ip_addr[] = {
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0x5c008000, /* 00 stgenc */
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0x54000000, /* 01 bkpsram */
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@ -163,8 +270,10 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
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int offset, shift;
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u32 addr, status, decprot[ETZPC_DECPROT_NB];
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if (IS_ENABLED(CONFIG_STM32MP13x))
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return 0;
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if (IS_ENABLED(CONFIG_STM32MP13x)) {
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array = stm32mp13_ip_addr;
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array_size = ARRAY_SIZE(stm32mp13_ip_addr);
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}
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if (IS_ENABLED(CONFIG_STM32MP15x)) {
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array = stm32mp15_ip_addr;
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@ -253,6 +362,43 @@ static void stm32_fdt_disable_optee(void *blob)
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}
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}
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static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
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{
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switch (cpu) {
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case CPU_STM32MP131Fxx:
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case CPU_STM32MP131Dxx:
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case CPU_STM32MP131Cxx:
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case CPU_STM32MP131Axx:
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stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name);
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stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name);
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fallthrough;
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case CPU_STM32MP133Fxx:
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case CPU_STM32MP133Dxx:
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case CPU_STM32MP133Cxx:
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case CPU_STM32MP133Axx:
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stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name);
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stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp",
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name);
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stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name);
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break;
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default:
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break;
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}
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switch (cpu) {
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case CPU_STM32MP135Dxx:
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case CPU_STM32MP135Axx:
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case CPU_STM32MP133Dxx:
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case CPU_STM32MP133Axx:
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case CPU_STM32MP131Dxx:
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case CPU_STM32MP131Axx:
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stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name);
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break;
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default:
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break;
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}
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}
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static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
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{
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u32 pkg;
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@ -345,6 +491,9 @@ int ft_system_setup(void *blob, struct bd_info *bd)
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cpu = get_cpu_type();
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get_soc_name(name);
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if (IS_ENABLED(CONFIG_STM32MP13x))
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stm32mp13_fdt_fixup(blob, soc, cpu, name);
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if (IS_ENABLED(CONFIG_STM32MP15x)) {
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stm32mp15_fdt_fixup(blob, soc, cpu, name);
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