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arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines

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These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár 2021-09-24 22:59:22 +02:00 committed by Stefan Roese
parent 28c935b5ee
commit de72930433
1 changed files with 1 additions and 1 deletions
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arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
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@ -12,7 +12,7 @@
/* Direct access to PEX0 Root Port's PCIe Capability structure */
#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
/* PEX_CAPABILITIES_REG fields */
/* SOC_CONTROL_REG1 fields */
#define PCIE0_ENABLE_OFFS 0
#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
#define PCIE1_ENABLE_OFFS 1