arm: dts: update DTS files for meson-gxbb and odroid-c2
Import DTS files and dt-bindings includes from Linux 4.8-rc1. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Beniamino Galvani
Tom Rini
parent
2c936374c8
commit
dd83840e5e
@ -45,6 +45,7 @@
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/dts-v1/;
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#include "meson-gxbb.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
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@ -62,8 +63,26 @@
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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blue {
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label = "c2:blue:alive";
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gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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default-state = "off";
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};
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};
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};
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&uart_AO {
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status = "okay";
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pinctrl-0 = <&uart_ao_a_pins>;
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pinctrl-names = "default";
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};
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ðmac {
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status = "okay";
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pinctrl-0 = <ð_pins>;
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pinctrl-names = "default";
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};
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@ -43,6 +43,8 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/meson-gxbb-gpio.h>
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#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
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/ {
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compatible = "amlogic,meson-gxbb";
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@ -129,13 +131,35 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
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reset: reset-controller@4404 {
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compatible = "amlogic,meson-gxbb-reset";
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reg = <0x0 0x04404 0x0 0x20>;
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#reset-cells = <1>;
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};
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uart_A: serial@84c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x084c0 0x0 0x14>;
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reg = <0x0 0x84c0 0x0 0x14>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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uart_B: serial@84dc {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x84dc 0x0 0x14>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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uart_C: serial@8700 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x8700 0x0 0x14>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>;
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status = "disabled";
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};
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};
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gic: interrupt-controller@c4301000 {
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@ -158,6 +182,29 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
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pinctrl_aobus: pinctrl@14 {
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compatible = "amlogic,meson-gxbb-aobus-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio_ao: bank@14 {
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reg = <0x0 0x00014 0x0 0x8>,
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<0x0 0x0002c 0x0 0x4>,
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<0x0 0x00024 0x0 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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uart_ao_a_pins: uart_ao_a {
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mux {
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groups = "uart_tx_ao_a", "uart_rx_ao_a";
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function = "uart_ao";
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};
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};
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};
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uart_AO: serial@4c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x0 0x004c0 0x0 0x14>;
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@ -167,6 +214,115 @@
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};
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};
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periphs: periphs@c8834000 {
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compatible = "simple-bus";
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reg = <0x0 0xc8834000 0x0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
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rng {
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compatible = "amlogic,meson-rng";
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reg = <0x0 0x0 0x0 0x4>;
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};
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pinctrl_periphs: pinctrl@4b0 {
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compatible = "amlogic,meson-gxbb-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: bank@4b0 {
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reg = <0x0 0x004b0 0x0 0x28>,
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<0x0 0x004e8 0x0 0x14>,
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<0x0 0x00120 0x0 0x14>,
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<0x0 0x00430 0x0 0x40>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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emmc_pins: emmc {
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mux {
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groups = "emmc_nand_d07",
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"emmc_cmd",
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"emmc_clk";
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function = "emmc";
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};
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};
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sdcard_pins: sdcard {
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mux {
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groups = "sdcard_d0",
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"sdcard_d1",
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"sdcard_d2",
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"sdcard_d3",
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"sdcard_cmd",
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"sdcard_clk";
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function = "sdcard";
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};
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};
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uart_a_pins: uart_a {
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mux {
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groups = "uart_tx_a",
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"uart_rx_a";
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function = "uart_a";
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};
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};
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uart_b_pins: uart_b {
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mux {
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groups = "uart_tx_b",
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"uart_rx_b";
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function = "uart_b";
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};
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};
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uart_c_pins: uart_c {
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mux {
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groups = "uart_tx_c",
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"uart_rx_c";
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function = "uart_c";
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};
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};
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eth_pins: eth_c {
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mux {
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groups = "eth_mdio",
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"eth_mdc",
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"eth_clk_rx_clk",
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"eth_rx_dv",
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"eth_rxd0",
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"eth_rxd1",
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"eth_rxd2",
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"eth_rxd3",
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"eth_rgmii_tx_clk",
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"eth_tx_en",
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"eth_txd0",
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"eth_txd1",
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"eth_txd2",
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"eth_txd3";
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function = "eth";
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};
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};
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};
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};
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hiubus: hiubus@c883c000 {
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compatible = "simple-bus";
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reg = <0x0 0xc883c000 0x0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
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clkc: clock-controller@0 {
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compatible = "amlogic,gxbb-clkc";
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#clock-cells = <1>;
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reg = <0x0 0x0 0x0 0x3db>;
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};
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};
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apb: apb@d0000000 {
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compatible = "simple-bus";
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reg = <0x0 0xd0000000 0x0 0x200000>;
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@ -174,5 +330,17 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
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};
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ethmac: ethernet@c9410000 {
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compatible = "amlogic,meson6-dwmac", "snps,dwmac";
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reg = <0x0 0xc9410000 0x0 0x10000
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0x0 0xc8834540 0x0 0x4>;
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interrupts = <0 8 1>;
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interrupt-names = "macirq";
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clocks = <&xtal>;
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clock-names = "stmmaceth";
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phy-mode = "rgmii";
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status = "disabled";
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};
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};
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};
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154
include/dt-bindings/gpio/meson-gxbb-gpio.h
Normal file
154
include/dt-bindings/gpio/meson-gxbb-gpio.h
Normal file
@ -0,0 +1,154 @@
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/*
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* GPIO definitions for Amlogic Meson GXBB SoCs
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*
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* Copyright (C) 2016 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
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#define _DT_BINDINGS_MESON_GXBB_GPIO_H
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#define GPIOAO_0 0
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#define GPIOAO_1 1
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#define GPIOAO_2 2
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#define GPIOAO_3 3
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#define GPIOAO_4 4
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#define GPIOAO_5 5
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#define GPIOAO_6 6
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#define GPIOAO_7 7
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#define GPIOAO_8 8
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#define GPIOAO_9 9
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#define GPIOAO_10 10
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#define GPIOAO_11 11
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#define GPIOAO_12 12
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#define GPIOAO_13 13
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#define GPIOZ_0 0
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#define GPIOZ_1 1
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#define GPIOZ_2 2
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#define GPIOZ_3 3
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#define GPIOZ_4 4
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#define GPIOZ_5 5
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#define GPIOZ_6 6
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#define GPIOZ_7 7
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#define GPIOZ_8 8
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#define GPIOZ_9 9
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#define GPIOZ_10 10
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#define GPIOZ_11 11
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#define GPIOZ_12 12
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#define GPIOZ_13 13
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#define GPIOZ_14 14
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#define GPIOZ_15 15
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#define GPIOH_0 16
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#define GPIOH_1 17
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#define GPIOH_2 18
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#define GPIOH_3 19
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#define BOOT_0 20
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#define BOOT_1 21
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#define BOOT_2 22
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#define BOOT_3 23
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#define BOOT_4 24
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#define BOOT_5 25
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#define BOOT_6 26
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#define BOOT_7 27
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#define BOOT_8 28
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#define BOOT_9 29
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#define BOOT_10 30
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#define BOOT_11 31
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#define BOOT_12 32
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#define BOOT_13 33
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#define BOOT_14 34
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#define BOOT_15 35
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#define BOOT_16 36
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#define BOOT_17 37
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#define CARD_0 38
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#define CARD_1 39
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#define CARD_2 40
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#define CARD_3 41
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#define CARD_4 42
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#define CARD_5 43
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#define CARD_6 44
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#define GPIODV_0 45
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#define GPIODV_1 46
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#define GPIODV_2 47
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#define GPIODV_3 48
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#define GPIODV_4 49
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#define GPIODV_5 50
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#define GPIODV_6 51
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#define GPIODV_7 52
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#define GPIODV_8 53
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#define GPIODV_9 54
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#define GPIODV_10 55
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#define GPIODV_11 56
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#define GPIODV_12 57
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#define GPIODV_13 58
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#define GPIODV_14 59
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#define GPIODV_15 60
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#define GPIODV_16 61
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#define GPIODV_17 62
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#define GPIODV_18 63
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#define GPIODV_19 64
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#define GPIODV_20 65
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#define GPIODV_21 66
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#define GPIODV_22 67
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#define GPIODV_23 68
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#define GPIODV_24 69
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#define GPIODV_25 70
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#define GPIODV_26 71
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#define GPIODV_27 72
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#define GPIODV_28 73
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#define GPIODV_29 74
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#define GPIOY_0 75
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#define GPIOY_1 76
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#define GPIOY_2 77
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#define GPIOY_3 78
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#define GPIOY_4 79
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#define GPIOY_5 80
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#define GPIOY_6 81
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#define GPIOY_7 82
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#define GPIOY_8 83
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#define GPIOY_9 84
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#define GPIOY_10 85
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#define GPIOY_11 86
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#define GPIOY_12 87
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#define GPIOY_13 88
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#define GPIOY_14 89
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#define GPIOY_15 90
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#define GPIOY_16 91
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#define GPIOX_0 92
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#define GPIOX_1 93
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#define GPIOX_2 94
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#define GPIOX_3 95
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#define GPIOX_4 96
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#define GPIOX_5 97
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#define GPIOX_6 98
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#define GPIOX_7 99
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#define GPIOX_8 100
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#define GPIOX_9 101
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#define GPIOX_10 102
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#define GPIOX_11 103
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#define GPIOX_12 104
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#define GPIOX_13 105
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#define GPIOX_14 106
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#define GPIOX_15 107
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#define GPIOX_16 108
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#define GPIOX_17 109
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#define GPIOX_18 110
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#define GPIOX_19 111
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#define GPIOX_20 112
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#define GPIOX_21 113
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#define GPIOX_22 114
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#define GPIOCLK_0 115
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#define GPIOCLK_1 116
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#define GPIOCLK_2 117
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#define GPIOCLK_3 118
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#define GPIO_TEST_N 119
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#endif
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210
include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
Normal file
210
include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
Normal file
@ -0,0 +1,210 @@
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of version 2 of the GNU General Public License as
|
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* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
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* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
* The full GNU General Public License is included in this distribution
|
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* in the file called COPYING.
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
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* Copyright (c) 2016 BayLibre, SAS.
|
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
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* are met:
|
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*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
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/* RESET0 */
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#define RESET_HIU 0
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/* 1 */
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#define RESET_DOS_RESET 2
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#define RESET_DDR_TOP 3
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#define RESET_DCU_RESET 4
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#define RESET_VIU 5
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#define RESET_AIU 6
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#define RESET_VID_PLL_DIV 7
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/* 8 */
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#define RESET_PMUX 9
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#define RESET_VENC 10
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#define RESET_ASSIST 11
|
||||
#define RESET_AFIFO2 12
|
||||
#define RESET_VCBUS 13
|
||||
/* 14 */
|
||||
/* 15 */
|
||||
#define RESET_GIC 16
|
||||
#define RESET_CAPB3_DECODE 17
|
||||
#define RESET_NAND_CAPB3 18
|
||||
#define RESET_HDMITX_CAPB3 19
|
||||
#define RESET_MALI_CAPB3 20
|
||||
#define RESET_DOS_CAPB3 21
|
||||
#define RESET_SYS_CPU_CAPB3 22
|
||||
#define RESET_CBUS_CAPB3 23
|
||||
#define RESET_AHB_CNTL 24
|
||||
#define RESET_AHB_DATA 25
|
||||
#define RESET_VCBUS_CLK81 26
|
||||
#define RESET_MMC 27
|
||||
#define RESET_MIPI_0 28
|
||||
#define RESET_MIPI_1 29
|
||||
#define RESET_MIPI_2 30
|
||||
#define RESET_MIPI_3 31
|
||||
/* RESET1 */
|
||||
#define RESET_CPPM 32
|
||||
#define RESET_DEMUX 33
|
||||
#define RESET_USB_OTG 34
|
||||
#define RESET_DDR 35
|
||||
#define RESET_AO_RESET 36
|
||||
#define RESET_BT656 37
|
||||
#define RESET_AHB_SRAM 38
|
||||
/* 39 */
|
||||
#define RESET_PARSER 40
|
||||
#define RESET_BLKMV 41
|
||||
#define RESET_ISA 42
|
||||
#define RESET_ETHERNET 43
|
||||
#define RESET_SD_EMMC_A 44
|
||||
#define RESET_SD_EMMC_B 45
|
||||
#define RESET_SD_EMMC_C 46
|
||||
#define RESET_ROM_BOOT 47
|
||||
#define RESET_SYS_CPU_0 48
|
||||
#define RESET_SYS_CPU_1 49
|
||||
#define RESET_SYS_CPU_2 50
|
||||
#define RESET_SYS_CPU_3 51
|
||||
#define RESET_SYS_CPU_CORE_0 52
|
||||
#define RESET_SYS_CPU_CORE_1 53
|
||||
#define RESET_SYS_CPU_CORE_2 54
|
||||
#define RESET_SYS_CPU_CORE_3 55
|
||||
#define RESET_SYS_PLL_DIV 56
|
||||
#define RESET_SYS_CPU_AXI 57
|
||||
#define RESET_SYS_CPU_L2 58
|
||||
#define RESET_SYS_CPU_P 59
|
||||
#define RESET_SYS_CPU_MBIST 60
|
||||
/* 61 */
|
||||
/* 62 */
|
||||
/* 63 */
|
||||
/* RESET2 */
|
||||
#define RESET_VD_RMEM 64
|
||||
#define RESET_AUDIN 65
|
||||
#define RESET_HDMI_TX 66
|
||||
/* 67 */
|
||||
/* 68 */
|
||||
/* 69 */
|
||||
#define RESET_GE2D 70
|
||||
#define RESET_PARSER_REG 71
|
||||
#define RESET_PARSER_FETCH 72
|
||||
#define RESET_PARSER_CTL 73
|
||||
#define RESET_PARSER_TOP 74
|
||||
/* 75 */
|
||||
/* 76 */
|
||||
#define RESET_AO_CPU_RESET 77
|
||||
#define RESET_MALI 78
|
||||
#define RESET_HDMI_SYSTEM_RESET 79
|
||||
/* 80-95 */
|
||||
/* RESET3 */
|
||||
#define RESET_RING_OSCILLATOR 96
|
||||
#define RESET_SYS_CPU 97
|
||||
#define RESET_EFUSE 98
|
||||
#define RESET_SYS_CPU_BVCI 99
|
||||
#define RESET_AIFIFO 100
|
||||
#define RESET_TVFE 101
|
||||
#define RESET_AHB_BRIDGE_CNTL 102
|
||||
/* 103 */
|
||||
#define RESET_AUDIO_DAC 104
|
||||
#define RESET_DEMUX_TOP 105
|
||||
#define RESET_DEMUX_DES 106
|
||||
#define RESET_DEMUX_S2P_0 107
|
||||
#define RESET_DEMUX_S2P_1 108
|
||||
#define RESET_DEMUX_RESET_0 109
|
||||
#define RESET_DEMUX_RESET_1 110
|
||||
#define RESET_DEMUX_RESET_2 111
|
||||
/* 112-127 */
|
||||
/* RESET4 */
|
||||
/* 128 */
|
||||
/* 129 */
|
||||
/* 130 */
|
||||
/* 131 */
|
||||
#define RESET_DVIN_RESET 132
|
||||
#define RESET_RDMA 133
|
||||
#define RESET_VENCI 134
|
||||
#define RESET_VENCP 135
|
||||
/* 136 */
|
||||
#define RESET_VDAC 137
|
||||
#define RESET_RTC 138
|
||||
/* 139 */
|
||||
#define RESET_VDI6 140
|
||||
#define RESET_VENCL 141
|
||||
#define RESET_I2C_MASTER_2 142
|
||||
#define RESET_I2C_MASTER_1 143
|
||||
/* 144-159 */
|
||||
/* RESET5 */
|
||||
/* 160-191 */
|
||||
/* RESET6 */
|
||||
#define RESET_PERIPHS_GENERAL 192
|
||||
#define RESET_PERIPHS_SPICC 193
|
||||
#define RESET_PERIPHS_SMART_CARD 194
|
||||
#define RESET_PERIPHS_SAR_ADC 195
|
||||
#define RESET_PERIPHS_I2C_MASTER_0 196
|
||||
#define RESET_SANA 197
|
||||
/* 198 */
|
||||
#define RESET_PERIPHS_STREAM_INTERFACE 199
|
||||
#define RESET_PERIPHS_SDIO 200
|
||||
#define RESET_PERIPHS_UART_0 201
|
||||
#define RESET_PERIPHS_UART_1_2 202
|
||||
#define RESET_PERIPHS_ASYNC_0 203
|
||||
#define RESET_PERIPHS_ASYNC_1 204
|
||||
#define RESET_PERIPHS_SPI_0 205
|
||||
#define RESET_PERIPHS_SDHC 206
|
||||
#define RESET_UART_SLIP 207
|
||||
/* 208-223 */
|
||||
/* RESET7 */
|
||||
#define RESET_USB_DDR_0 224
|
||||
#define RESET_USB_DDR_1 225
|
||||
#define RESET_USB_DDR_2 226
|
||||
#define RESET_USB_DDR_3 227
|
||||
/* 228 */
|
||||
#define RESET_DEVICE_MMC_ARB 229
|
||||
/* 230 */
|
||||
#define RESET_VID_LOCK 231
|
||||
#define RESET_A9_DMC_PIPEL 232
|
||||
/* 233-255 */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user