phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's possible to select one of these two inputs from device tree. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
This commit is contained in:
Aswath Govindraju
Tom Rini
parent
6f46c7441a
commit
dd75927059
@ -13,6 +13,7 @@
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*/
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#include <common.h>
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#include <clk.h>
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#include <linux/clk-provider.h>
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#include <generic-phy.h>
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#include <reset.h>
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#include <dm/device.h>
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@ -24,11 +25,13 @@
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#include <dm/devres.h>
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#include <linux/io.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/phy/phy-cadence.h>
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#include <regmap.h>
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/* PHY register offsets */
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#define SIERRA_COMMON_CDB_OFFSET 0x0
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#define SIERRA_MACRO_ID_REG 0x0
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#define SIERRA_CMN_PLLLC_GEN_PREG 0x42
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#define SIERRA_CMN_PLLLC_MODE_PREG 0x48
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#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
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#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
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@ -36,6 +39,9 @@
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#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
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#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
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#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62
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#define SIERRA_CMN_REFRCV_PREG 0x98
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#define SIERRA_CMN_REFRCV1_PREG 0xB8
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#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
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#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
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(0x4000 + ((ln) * (0x800 >> (2 - (offset)))))
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@ -147,13 +153,18 @@
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#define SIERRA_MAX_LANES 16
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#define PLL_LOCK_TIME 100
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#define CDNS_SIERRA_INPUT_CLOCKS 3
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#define CDNS_SIERRA_INPUT_CLOCKS 5
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enum cdns_sierra_clock_input {
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PHY_CLK,
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CMN_REFCLK_DIG_DIV,
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CMN_REFCLK1_DIG_DIV,
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PLL0_REFCLK,
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PLL1_REFCLK,
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};
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#define SIERRA_NUM_CMN_PLLC 2
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#define SIERRA_NUM_CMN_PLLC_PARENTS 2
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static const struct reg_field macro_id_type =
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REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
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static const struct reg_field phy_pll_cfg_1 =
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@ -161,6 +172,44 @@ static const struct reg_field phy_pll_cfg_1 =
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static const struct reg_field pllctrl_lock =
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REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
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static const char * const clk_names[] = {
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[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
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[CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
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};
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enum cdns_sierra_cmn_plllc {
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CMN_PLLLC,
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CMN_PLLLC1,
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};
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struct cdns_sierra_pll_mux_reg_fields {
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struct reg_field pfdclk_sel_preg;
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struct reg_field plllc1en_field;
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struct reg_field termen_field;
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};
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static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {
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[CMN_PLLLC] = {
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.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
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.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
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.termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
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},
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[CMN_PLLLC1] = {
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.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
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.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
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.termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
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},
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};
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struct cdns_sierra_pll_mux {
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struct cdns_sierra_phy *sp;
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struct clk *clk;
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struct clk *parent_clks[2];
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struct regmap_field *pfdclk_sel_preg;
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struct regmap_field *plllc1en_field;
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struct regmap_field *termen_field;
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};
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#define reset_control_assert(rst) cdns_reset_assert(rst)
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#define reset_control_deassert(rst) cdns_reset_deassert(rst)
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#define reset_control reset_ctl
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@ -191,12 +240,6 @@ struct cdns_sierra_data {
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struct cdns_reg_pairs *usb_ln_vals;
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};
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struct cdns_regmap_cdb_context {
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struct udevice *dev;
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void __iomem *base;
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u8 reg_offset_shift;
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};
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struct cdns_sierra_phy {
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struct udevice *dev;
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void *base;
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@ -211,6 +254,9 @@ struct cdns_sierra_phy {
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struct regmap_field *macro_id_type;
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struct regmap_field *phy_pll_cfg_1;
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struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
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struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
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struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
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struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
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struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
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int nsubnodes;
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u32 num_lanes;
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@ -348,6 +394,116 @@ static const struct phy_ops ops = {
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.reset = cdns_sierra_phy_reset,
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};
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struct cdns_sierra_pll_mux_sel {
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enum cdns_sierra_cmn_plllc mux_sel;
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u32 table[2];
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const char *node_name;
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u32 num_parents;
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u32 parents[2];
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};
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static struct cdns_sierra_pll_mux_sel pll_clk_mux_sel[] = {
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{
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.num_parents = 2,
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.parents = { PLL0_REFCLK, PLL1_REFCLK },
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.mux_sel = CMN_PLLLC,
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.table = { 0, 1 },
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.node_name = "pll_cmnlc",
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},
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{
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.num_parents = 2,
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.parents = { PLL1_REFCLK, PLL0_REFCLK },
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.mux_sel = CMN_PLLLC1,
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.table = { 1, 0 },
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.node_name = "pll_cmnlc1",
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},
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};
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static int cdns_sierra_pll_mux_set_parent(struct clk *clk, struct clk *parent)
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{
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struct udevice *dev = clk->dev;
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struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
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struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev);
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struct cdns_sierra_phy *sp = priv->sp;
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int ret;
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int i;
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for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
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if (parent->dev == priv->parent_clks[i]->dev)
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break;
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}
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if (i == ARRAY_SIZE(priv->parent_clks))
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return -EINVAL;
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ret = regmap_field_write(sp->cmn_refrcv_refclk_plllc1en_preg[data[clk->id].mux_sel], i);
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ret |= regmap_field_write(sp->cmn_refrcv_refclk_termen_preg[data[clk->id].mux_sel], i);
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ret |= regmap_field_write(sp->cmn_plllc_pfdclk1_sel_preg[data[clk->id].mux_sel],
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data[clk->id].table[i]);
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return ret;
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}
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static const struct clk_ops cdns_sierra_pll_mux_ops = {
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.set_parent = cdns_sierra_pll_mux_set_parent,
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};
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int cdns_sierra_pll_mux_probe(struct udevice *dev)
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{
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struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
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struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
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struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev);
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struct clk *clk;
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int i, j;
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for (j = 0; j < SIERRA_NUM_CMN_PLLC; j++) {
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for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
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clk = sp->input_clks[data[j].parents[i]];
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if (IS_ERR_OR_NULL(clk)) {
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dev_err(dev, "No parent clock for PLL mux clocks\n");
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return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT;
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}
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priv->parent_clks[i] = clk;
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}
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}
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priv->sp = dev_get_priv(dev->parent);
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return 0;
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}
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U_BOOT_DRIVER(cdns_sierra_pll_mux_clk) = {
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.name = "cdns_sierra_mux_clk",
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.id = UCLASS_CLK,
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.priv_auto = sizeof(struct cdns_sierra_pll_mux),
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.ops = &cdns_sierra_pll_mux_ops,
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.probe = cdns_sierra_pll_mux_probe,
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.plat_auto = sizeof(struct cdns_sierra_pll_mux_sel) * SIERRA_NUM_CMN_PLLC,
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};
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static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
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{
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struct udevice *dev = sp->dev;
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struct driver *cdns_sierra_clk_drv;
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struct cdns_sierra_pll_mux_sel *data = pll_clk_mux_sel;
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int i, rc;
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cdns_sierra_clk_drv = lists_driver_lookup_name("cdns_sierra_mux_clk");
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if (!cdns_sierra_clk_drv) {
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dev_err(dev, "Can not find driver 'cdns_sierra_mux_clk'\n");
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return -ENOENT;
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}
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rc = device_bind(dev, cdns_sierra_clk_drv, "pll_mux_clk",
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data, dev_ofnode(dev), NULL);
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if (rc) {
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dev_err(dev, "cannot bind driver for clock %s\n",
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clk_names[i]);
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}
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return 0;
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}
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static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
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ofnode child)
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{
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@ -382,6 +538,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
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{
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struct udevice *dev = sp->dev;
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struct regmap_field *field;
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struct reg_field reg_field;
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struct regmap *regmap;
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int i;
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@ -393,6 +550,32 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
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}
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sp->macro_id_type = field;
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for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {
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reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;
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field = devm_regmap_field_alloc(dev, regmap, reg_field);
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if (IS_ERR(field)) {
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dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);
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return PTR_ERR(field);
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}
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sp->cmn_plllc_pfdclk1_sel_preg[i] = field;
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reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;
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field = devm_regmap_field_alloc(dev, regmap, reg_field);
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if (IS_ERR(field)) {
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dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);
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return PTR_ERR(field);
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}
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sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;
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reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;
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field = devm_regmap_field_alloc(dev, regmap, reg_field);
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if (IS_ERR(field)) {
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dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);
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return PTR_ERR(field);
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}
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sp->cmn_refrcv_refclk_termen_preg[i] = field;
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}
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regmap = sp->regmap_phy_config_ctrl;
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field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
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if (IS_ERR(field)) {
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@ -482,6 +665,22 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
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}
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sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
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clk = devm_clk_get_optional(dev, "pll0_refclk");
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if (IS_ERR(clk)) {
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dev_err(dev, "pll0_refclk clock not found\n");
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ret = PTR_ERR(clk);
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return ret;
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}
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sp->input_clks[PLL0_REFCLK] = clk;
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clk = devm_clk_get_optional(dev, "pll1_refclk");
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if (IS_ERR(clk)) {
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dev_err(dev, "pll1_refclk clock not found\n");
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ret = PTR_ERR(clk);
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return ret;
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}
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sp->input_clks[PLL1_REFCLK] = clk;
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return 0;
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}
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@ -572,7 +771,7 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
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struct cdns_sierra_phy *sp = dev_get_priv(dev);
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struct cdns_sierra_data *data;
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unsigned int id_value;
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int ret, node = 0;
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int ret;
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sp->dev = dev;
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@ -600,11 +799,9 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
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if (ret)
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return ret;
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sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
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if (IS_ERR(sp->phy_rst)) {
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dev_err(dev, "failed to get reset\n");
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return PTR_ERR(sp->phy_rst);
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}
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ret = cdns_sierra_pll_bind_of_clocks(sp);
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if (ret)
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return ret;
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ret = cdns_sierra_phy_get_resets(sp, dev);
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if (ret)
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