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ARM: tegra: pinctrl: remove vddio

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This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2014-03-21 12:28:50 -06:00 committed by Tom Warren
parent 0d2c0d5788
commit dd45948dd7
8 changed files with 0 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/cpu/tegra114-common/pinmux.c
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@ -24,7 +24,6 @@
struct tegra_pingroup_desc { struct tegra_pingroup_desc {
const char *name; const char *name;
enum pmux_func funcs[4]; enum pmux_func funcs[4];
enum pmux_vddio vddio;
enum pmux_pin_io io; enum pmux_pin_io io;
}; };
@ -54,7 +53,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */ /* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \ { \
.vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \ .funcs = { \
PMUX_FUNC_ ## f0, \ PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \ PMUX_FUNC_ ## f1, \

2
arch/arm/cpu/tegra124-common/pinmux.c
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@ -15,7 +15,6 @@
struct tegra_pingroup_desc { struct tegra_pingroup_desc {
const char *name; const char *name;
enum pmux_func funcs[4]; enum pmux_func funcs[4];
enum pmux_vddio vddio;
enum pmux_pin_io io; enum pmux_pin_io io;
}; };
@ -45,7 +44,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */ /* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \ { \
.vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \ .funcs = { \
PMUX_FUNC_ ## f0, \ PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \ PMUX_FUNC_ ## f1, \

2
arch/arm/cpu/tegra20-common/pinmux.c
View File

@ -259,7 +259,6 @@ enum pmux_pullid {
struct tegra_pingroup_desc { struct tegra_pingroup_desc {
const char *name; const char *name;
enum pmux_func funcs[4]; enum pmux_func funcs[4];
enum pmux_vddio vddio;
enum pmux_ctlid ctl_id; enum pmux_ctlid ctl_id;
enum pmux_pullid pull_id; enum pmux_pullid pull_id;
}; };
@ -286,7 +285,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */ /* Convenient macro for defining pin group properties */
#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \ #define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
{ \ { \
.vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \ .funcs = { \
PMUX_FUNC_ ## f0, \ PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \ PMUX_FUNC_ ## f1, \

2
arch/arm/cpu/tegra30-common/pinmux.c
View File

@ -24,7 +24,6 @@
struct tegra_pingroup_desc { struct tegra_pingroup_desc {
const char *name; const char *name;
enum pmux_func funcs[4]; enum pmux_func funcs[4];
enum pmux_vddio vddio;
enum pmux_pin_io io; enum pmux_pin_io io;
}; };
@ -53,7 +52,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */ /* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \ { \
.vddio = PMUX_VDDIO_ ## vdd, \
.funcs = { \ .funcs = { \
PMUX_FUNC_ ## f0, \ PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \ PMUX_FUNC_ ## f1, \

21
arch/arm/include/asm/arch-tegra114/pinmux.h
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@ -449,27 +449,6 @@ enum pmux_pin_rcv_sel {
(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \ (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
PMUX_VDDIO_LCD,
PMUX_VDDIO_VI,
PMUX_VDDIO_UART,
PMUX_VDDIO_DDR,
PMUX_VDDIO_NAND,
PMUX_VDDIO_SYS,
PMUX_VDDIO_AUDIO,
PMUX_VDDIO_SD,
PMUX_VDDIO_CAM,
PMUX_VDDIO_GMI,
PMUX_VDDIO_PEXCTL,
PMUX_VDDIO_SDMMC1,
PMUX_VDDIO_SDMMC3,
PMUX_VDDIO_SDMMC4,
PMUX_VDDIO_NONE
};
#define PGRP_SLWF_NONE -1 #define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3 #define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE #define PGRP_SLWR_NONE PGRP_SLWF_NONE

21
arch/arm/include/asm/arch-tegra124/pinmux.h
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@ -458,27 +458,6 @@ enum pmux_pin_rcv_sel {
(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \ (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
PMUX_VDDIO_LCD,
PMUX_VDDIO_VI,
PMUX_VDDIO_UART,
PMUX_VDDIO_DDR,
PMUX_VDDIO_NAND,
PMUX_VDDIO_SYS,
PMUX_VDDIO_AUDIO,
PMUX_VDDIO_SD,
PMUX_VDDIO_CAM,
PMUX_VDDIO_GMI,
PMUX_VDDIO_PEXCTL,
PMUX_VDDIO_SDMMC1,
PMUX_VDDIO_SDMMC3,
PMUX_VDDIO_SDMMC4,
PMUX_VDDIO_NONE
};
#define PGRP_SLWF_NONE -1 #define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3 #define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE #define PGRP_SLWR_NONE PGRP_SLWF_NONE

15
arch/arm/include/asm/arch-tegra20/pinmux.h
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@ -257,21 +257,6 @@ enum pmux_tristate {
PMUX_TRI_TRISTATE = 1, PMUX_TRI_TRISTATE = 1,
}; };
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
PMUX_VDDIO_LCD,
PMUX_VDDIO_VI,
PMUX_VDDIO_UART,
PMUX_VDDIO_DDR,
PMUX_VDDIO_NAND,
PMUX_VDDIO_SYS,
PMUX_VDDIO_AUDIO,
PMUX_VDDIO_SD,
PMUX_VDDIO_NONE
};
enum { enum {
PMUX_TRISTATE_REGS = 4, PMUX_TRISTATE_REGS = 4,
PMUX_MUX_REGS = 7, PMUX_MUX_REGS = 7,

21
arch/arm/include/asm/arch-tegra30/pinmux.h
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@ -509,27 +509,6 @@ enum pmux_pin_ioreset {
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
PMUX_VDDIO_LCD,
PMUX_VDDIO_VI,
PMUX_VDDIO_UART,
PMUX_VDDIO_DDR,
PMUX_VDDIO_NAND,
PMUX_VDDIO_SYS,
PMUX_VDDIO_AUDIO,
PMUX_VDDIO_SD,
PMUX_VDDIO_CAM,
PMUX_VDDIO_GMI,
PMUX_VDDIO_PEXCTL,
PMUX_VDDIO_SDMMC1,
PMUX_VDDIO_SDMMC3,
PMUX_VDDIO_SDMMC4,
PMUX_VDDIO_NONE
};
#define PGRP_SLWF_NONE -1 #define PGRP_SLWF_NONE -1
#define PGRP_SLWF_MAX 3 #define PGRP_SLWF_MAX 3
#define PGRP_SLWR_NONE PGRP_SLWF_NONE #define PGRP_SLWR_NONE PGRP_SLWF_NONE