net: sh-eth: Add to Kconfig and convert
This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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@ -24,7 +24,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_PHY_MICREL=y
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CONFIG_BAUDRATE=38400
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CONFIG_SCIF_CONSOLE=y
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@ -25,6 +25,7 @@ CONFIG_CMD_PING=y
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# CONFIG_CMD_MISC is not set
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -27,6 +27,7 @@ CONFIG_CMD_PING=y
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# CONFIG_CMD_MISC is not set
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CONFIG_ENV_IS_IN_FLASH=y
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# CONFIG_MMC is not set
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_OF_LIBFDT=y
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@ -29,7 +29,8 @@ CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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@ -25,6 +25,7 @@ CONFIG_CMD_PING=y
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# CONFIG_CMD_MISC is not set
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -24,8 +24,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_BAUDRATE=38400
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USB=y
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@ -24,8 +24,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_BAUDRATE=38400
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USB=y
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@ -24,8 +24,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_BAUDRATE=38400
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USB=y
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@ -24,8 +24,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_BAUDRATE=38400
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USB=y
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@ -25,6 +25,7 @@ CONFIG_CMD_PING=y
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# CONFIG_CMD_MISC is not set
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -34,6 +34,7 @@ CONFIG_MMC=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -33,6 +33,7 @@ CONFIG_MMC=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -33,6 +33,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_MMC=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -26,6 +26,7 @@ CONFIG_CMD_PING=y
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CONFIG_CMD_JFFS2=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -24,8 +24,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_BAUDRATE=38400
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USB=y
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@ -24,8 +24,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_NETDEVICES=y
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CONFIG_SH_ETHER=y
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CONFIG_BAUDRATE=38400
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USB=y
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@ -276,6 +276,12 @@ config SUN8I_EMAC
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It can be found in H3/A64/A83T based SoCs and compatible with both
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External and Internal PHYs.
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config SH_ETHER
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bool "Renesas SH Ethernet MAC"
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select PHYLIB
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help
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This driver supports the Ethernet for Renesas SH and ARM SoCs.
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config XILINX_AXIEMAC
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depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
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select PHYLIB
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@ -44,7 +44,6 @@
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#define CONFIG_SPI_FLASH_QUAD
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@ -18,7 +18,6 @@
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
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#define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
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@ -88,7 +88,6 @@
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x0
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#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
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@ -44,7 +44,6 @@
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#define CONFIG_SH_I2C_CLOCK 41666666
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
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#define CONFIG_PHY_SMSC 1
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@ -77,7 +77,6 @@
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#define CONFIG_SYS_TMU_CLK_DIV 4
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (1)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
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#define CONFIG_BITBANGMII
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#define CONFIG_SH_QSPI
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SH_QSPI
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SH_QSPI
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SPI_FLASH_QUAD
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
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#define CONFIG_PHY_SMSC 1
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 18
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 18
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 1
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (1)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
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#define CONFIG_BITBANGMII
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#define CONFIG_SPI_FLASH_QUAD
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SPI_FLASH_QUAD
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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@ -1924,7 +1924,6 @@ CONFIG_SHOW_ACTIVITY
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CONFIG_SHOW_BOOT_PROGRESS
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CONFIG_SH_CMT_CLK_FREQ
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CONFIG_SH_DSP
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CONFIG_SH_ETHER
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CONFIG_SH_ETHER_ALIGNE_SIZE
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CONFIG_SH_ETHER_BASE_ADDR
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CONFIG_SH_ETHER_CACHE_INVALIDATE
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