powerpc: ppc4xx: remove board support for KAREF and METROBOX
These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
717a23b871
commit
dc9617e0ce
@ -226,12 +226,6 @@ config TARGET_ALPR
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config TARGET_P3P440
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bool "Support p3p440"
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config TARGET_KAREF
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bool "Support KAREF"
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config TARGET_METROBOX
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bool "Support METROBOX"
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config TARGET_XPEDITE1000
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bool "Support xpedite1000"
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@ -306,8 +300,6 @@ source "board/mpl/pip405/Kconfig"
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source "board/pcs440ep/Kconfig"
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source "board/prodrive/alpr/Kconfig"
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source "board/prodrive/p3p440/Kconfig"
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source "board/sandburst/karef/Kconfig"
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source "board/sandburst/metrobox/Kconfig"
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source "board/sbc405/Kconfig"
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source "board/sc3/Kconfig"
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source "board/t3corp/Kconfig"
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@ -1,493 +0,0 @@
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/*
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* (C) Copyright 2002-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
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* Add support for Am29F016D and dynamic switch setting.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Ported from Ebony flash support
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* Travis B. Sawyer
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* Sandburst Corporation
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DEBUGF(x...) printf(x)
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#else
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#define DEBUGF(x...)
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#endif /* DEBUG */
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
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{0xfff80000} /* Boot Flash */
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};
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static int write_word (flash_info_t *info, ulong dest, ulong data);
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#define ADDR0 0x5555
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#define ADDR1 0x2aaa
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#define FLASH_WORD_SIZE unsigned char
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long total_b = 0;
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unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
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unsigned short index = 0;
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int i;
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DEBUGF("\n");
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DEBUGF("FLASH: Index: %d\n", index);
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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flash_info[i].sector_count = -1;
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flash_info[i].size = 0;
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/* check whether the address is 0 */
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if (flash_addr_table[index][i] == 0) {
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continue;
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}
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/* call flash_get_size() to initialize sector address */
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size_b[i] = flash_get_size(
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(vu_long *)flash_addr_table[index][i], &flash_info[i]);
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flash_info[i].size = size_b[i];
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if (flash_info[i].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
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i, size_b[i], size_b[i]<<20);
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flash_info[i].sector_count = -1;
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flash_info[i].size = 0;
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}
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total_b += flash_info[i].size;
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}
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return total_b;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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int k;
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int size;
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int erased;
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volatile unsigned long *flash;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld KB in %d Sectors\n",
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info->size >> 10, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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/*
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* Check if whole sector is erased
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*/
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if (i != (info->sector_count-1))
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size = info->start[i+1] - info->start[i];
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else
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size = info->start[0] + info->size - info->start[i];
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erased = 1;
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flash = (volatile unsigned long *)info->start[i];
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size = size >> 2; /* divide by 4 for longword access */
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for (k=0; k<size; k++)
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{
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if (*flash++ != 0xffffffff)
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{
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erased = 0;
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break;
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}
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}
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s%s",
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info->start[i],
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erased ? " E" : " ",
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info->protect[i] ? "RO " : " "
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);
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}
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printf ("\n");
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return;
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}
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/*-----------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info)
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{
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short i;
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FLASH_WORD_SIZE value;
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ulong base = (ulong)addr;
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volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
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DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
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/* Write auto select command: read Manufacturer ID */
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udelay(10000);
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addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
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udelay(1000);
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addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
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udelay(1000);
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addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
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udelay(1000);
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value = addr2[0];
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DEBUGF("FLASH MANUFACT: %x\n", value);
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switch (value) {
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case (FLASH_WORD_SIZE)AMD_MANUFACT:
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info->flash_id = FLASH_MAN_AMD;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* no or unknown flash */
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}
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value = addr2[1]; /* device ID */
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DEBUGF("\nFLASH DEVICEID: %x\n", value);
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switch (value) {
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case (FLASH_WORD_SIZE)AMD_ID_LV040B:
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info->flash_id += FLASH_AM040;
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info->sector_count = 8;
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info->size = 0x00080000; /* => 512 kb */
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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return (0); /* => no or unknown flash */
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}
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/* set up sector start address table */
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if (info->flash_id == FLASH_AM040) {
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = base + (i * 0x00010000);
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} else {
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if (info->flash_id & FLASH_BTYPE) {
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/* set sector offsets for bottom boot block type */
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info->start[0] = base + 0x00000000;
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info->start[1] = base + 0x00004000;
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info->start[2] = base + 0x00006000;
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info->start[3] = base + 0x00008000;
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for (i = 4; i < info->sector_count; i++) {
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info->start[i] = base + (i * 0x00010000) - 0x00030000;
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}
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} else {
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/* set sector offsets for top boot block type */
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i = info->sector_count - 1;
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info->start[i--] = base + info->size - 0x00004000;
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info->start[i--] = base + info->size - 0x00006000;
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info->start[i--] = base + info->size - 0x00008000;
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for (; i >= 0; i--) {
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info->start[i] = base + i * 0x00010000;
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}
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}
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}
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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/* D0 = 1 if protected */
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addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
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info->protect[i] = 0;
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else
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info->protect[i] = addr2[2] & 1;
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}
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/* reset to return to reading data */
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addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
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/*
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* Prevent writes to uninitialized FLASH.
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*/
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if (info->flash_id != FLASH_UNKNOWN) {
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addr2 = (FLASH_WORD_SIZE *)info->start[0];
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*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
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}
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return (info->size);
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}
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int wait_for_DQ7(flash_info_t *info, int sect)
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{
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ulong start, now, last;
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
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start = get_timer (0);
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last = start;
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while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
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if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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return -1;
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}
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/* show that we're waiting */
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if ((now - last) > 1000) { /* every second */
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putc ('.');
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last = now;
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}
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}
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return 0;
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
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volatile FLASH_WORD_SIZE *addr2;
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int flag, prot, sect;
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int i;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("Can't erase unknown flash type - aborted\n");
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return 1;
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}
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prot = 0;
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for (sect=s_first; sect<=s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect<=s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
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DEBUGF("Erasing sector %p\n", addr2);
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
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addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
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addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
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addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
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addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
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addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
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addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
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for (i=0; i<50; i++)
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udelay(1000); /* wait 1 ms */
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} else {
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addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
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addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
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addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
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addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
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addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
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addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
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}
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/*
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* Wait for each sector to complete, it's more
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* reliable. According to AMD Spec, you must
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* issue all erase commands within a specified
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* timeout. This has been seen to fail, especially
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* if printf()s are included (for debug)!!
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*/
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wait_for_DQ7(info, sect);
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}
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}
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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/* wait at least 80us - let's wait 1 ms */
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udelay (1000);
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/* reset to read mode */
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addr = (FLASH_WORD_SIZE *)info->start[0];
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addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
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printf (" done\n");
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return 0;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong cp, wp, data;
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int i, l, rc;
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wp = (addr & ~3); /* get lower word aligned address */
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i=0, cp=wp; i<l; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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for (; i<4 && cnt>0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt==0 && i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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}
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/*
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* handle word aligned part
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*/
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while (cnt >= 4) {
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data = 0;
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for (i=0; i<4; ++i) {
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data = (data << 8) | *src++;
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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cnt -= 4;
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}
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if (cnt == 0) {
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return (0);
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}
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/*
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* handle unaligned tail bytes
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*/
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data = 0;
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for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
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data = (data << 8) | *src++;
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--cnt;
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}
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for (; i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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return (write_word(info, wp, data));
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}
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/*-----------------------------------------------------------------------
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* Write a word to Flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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static int write_word (flash_info_t * info, ulong dest, ulong data)
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{
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volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
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volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
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volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
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ulong start;
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int i;
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/* Check if Flash is (sufficiently) erased */
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if ((*((volatile FLASH_WORD_SIZE *) dest) &
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(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
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return (2);
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}
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for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
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int flag;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts ();
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|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
|
||||
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -1,349 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
#include "sb_common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
long int fixed_sdram (void);
|
||||
|
||||
/*************************************************************************
|
||||
* metrobox_get_master
|
||||
*
|
||||
* PRI_N - active low signal. If the GPIO pin is low we are the master
|
||||
*
|
||||
************************************************************************/
|
||||
int sbcommon_get_master(void)
|
||||
{
|
||||
ppc440_gpio_regs_t *gpio_regs;
|
||||
|
||||
gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
|
||||
|
||||
if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* metrobox_secondary_present
|
||||
*
|
||||
* Figure out if secondary/slave board is present
|
||||
*
|
||||
************************************************************************/
|
||||
int sbcommon_secondary_present(void)
|
||||
{
|
||||
ppc440_gpio_regs_t *gpio_regs;
|
||||
|
||||
gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
|
||||
|
||||
if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* sbcommon_get_serial_number
|
||||
*
|
||||
* Retrieve the board serial number via the mac address in eeprom
|
||||
*
|
||||
************************************************************************/
|
||||
unsigned short sbcommon_get_serial_number(void)
|
||||
{
|
||||
unsigned char buff[0x100];
|
||||
unsigned short sernum;
|
||||
|
||||
/* Get the board serial number from eeprom */
|
||||
/* Initialize I2C */
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
/* Read 256 bytes in EEPROM */
|
||||
i2c_read (0x50, 0, 1, buff, 0x100);
|
||||
|
||||
memcpy(&sernum, &buff[0xF4], 2);
|
||||
sernum /= 32;
|
||||
|
||||
return (sernum);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* sbcommon_fans
|
||||
*
|
||||
* Spin up fans 2 & 3 to get some air moving. OS will take care
|
||||
* of the rest. This is mostly a precaution...
|
||||
*
|
||||
* Assumes i2c bus 1 is ready.
|
||||
*
|
||||
************************************************************************/
|
||||
void sbcommon_fans(void)
|
||||
{
|
||||
/*
|
||||
* Attempt to turn on 2 of the fans...
|
||||
* Need to go through the bridge
|
||||
*/
|
||||
i2c_set_bus_num(1);
|
||||
puts ("FANS: ");
|
||||
|
||||
/* select fan4 through the bridge */
|
||||
i2c_reg_write(0x73, /* addr */
|
||||
0x00, /* reg */
|
||||
0x08); /* val = bus 4 */
|
||||
|
||||
/* Turn on FAN 4 */
|
||||
i2c_reg_write(0x2e,
|
||||
1,
|
||||
0x80);
|
||||
|
||||
i2c_reg_write(0x2e,
|
||||
0,
|
||||
0x19);
|
||||
|
||||
/* Deselect bus 4 on the bridge */
|
||||
i2c_reg_write(0x73,
|
||||
0x00,
|
||||
0x00);
|
||||
|
||||
/* select fan3 through the bridge */
|
||||
i2c_reg_write(0x73, /* addr */
|
||||
0x00, /* reg */
|
||||
0x04); /* val = bus 3 */
|
||||
|
||||
/* Turn on FAN 3 */
|
||||
i2c_reg_write(0x2e,
|
||||
1,
|
||||
0x80);
|
||||
|
||||
i2c_reg_write(0x2e,
|
||||
0,
|
||||
0x19);
|
||||
|
||||
/* Deselect bus 3 on the bridge */
|
||||
i2c_reg_write(0x73,
|
||||
0x00,
|
||||
0x00);
|
||||
|
||||
/* select fan2 through the bridge */
|
||||
i2c_reg_write(0x73, /* addr */
|
||||
0x00, /* reg */
|
||||
0x02); /* val = bus 4 */
|
||||
|
||||
/* Turn on FAN 2 */
|
||||
i2c_reg_write(0x2e,
|
||||
1,
|
||||
0x80);
|
||||
|
||||
i2c_reg_write(0x2e,
|
||||
0,
|
||||
0x19);
|
||||
|
||||
/* Deselect bus 2 on the bridge */
|
||||
i2c_reg_write(0x73,
|
||||
0x00,
|
||||
0x00);
|
||||
|
||||
/* select fan1 through the bridge */
|
||||
i2c_reg_write(0x73, /* addr */
|
||||
0x00, /* reg */
|
||||
0x01); /* val = bus 0 */
|
||||
|
||||
/* Turn on FAN 1 */
|
||||
i2c_reg_write(0x2e,
|
||||
1,
|
||||
0x80);
|
||||
|
||||
i2c_reg_write(0x2e,
|
||||
0,
|
||||
0x19);
|
||||
|
||||
/* Deselect bus 1 on the bridge */
|
||||
i2c_reg_write(0x73,
|
||||
0x00,
|
||||
0x00);
|
||||
|
||||
puts ("on\n");
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* initdram
|
||||
*
|
||||
* Initialize sdram
|
||||
*
|
||||
************************************************************************/
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
dram_size = spd_sdram ();
|
||||
#else
|
||||
dram_size = fixed_sdram ();
|
||||
#endif
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* testdram
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_SYS_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
|
||||
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf("Testing SDRAM: ");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("OK\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect.
|
||||
*
|
||||
* Assumes: 128 MB, non-ECC, non-registered
|
||||
* PLB @ 133 MHz
|
||||
*
|
||||
************************************************************************/
|
||||
long int fixed_sdram (void)
|
||||
{
|
||||
uint reg;
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup some default
|
||||
*------------------------------------------------------------------*/
|
||||
mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
|
||||
mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
|
||||
mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
|
||||
mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
|
||||
mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup for board-specific specific mem
|
||||
*------------------------------------------------------------------*/
|
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
||||
*/
|
||||
mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
|
||||
mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
|
||||
/* RA=10 RD=3 */
|
||||
mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
|
||||
mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
|
||||
mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
|
||||
udelay (400); /* Delay 200 usecs (min) */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Enable the controller, then wait for DCEN to complete
|
||||
*------------------------------------------------------------------*/
|
||||
mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
|
||||
for (;;) {
|
||||
mfsdram (SDRAM0_MCSTS, reg);
|
||||
if (reg & 0x80000000)
|
||||
break;
|
||||
}
|
||||
|
||||
return (128 * 1024 * 1024); /* 128 MB */
|
||||
}
|
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
||||
|
||||
/*************************************************************************
|
||||
* board_get_enetaddr
|
||||
*
|
||||
* Get the ethernet MAC address for the management ethernet from the
|
||||
* strap EEPROM. Note that is the BASE address for the range of
|
||||
* external ethernet MACs on the board. The base + 31 is the actual
|
||||
* mgmt mac address.
|
||||
*
|
||||
************************************************************************/
|
||||
|
||||
void board_get_enetaddr(int macaddr_idx, uchar *enet)
|
||||
{
|
||||
int i;
|
||||
unsigned short tmp;
|
||||
unsigned char buff[0x100], *cp;
|
||||
|
||||
if (0 == macaddr_idx) {
|
||||
|
||||
/* Initialize I2C */
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
/* Read 256 bytes in EEPROM */
|
||||
i2c_read (0x50, 0, 1, buff, 0x100);
|
||||
|
||||
cp = &buff[0xF0];
|
||||
|
||||
for (i = 0; i < 6; i++,cp++)
|
||||
enet[i] = *cp;
|
||||
|
||||
memcpy(&tmp, &enet[4], 2);
|
||||
tmp += 31;
|
||||
memcpy(&enet[4], &tmp, 2);
|
||||
|
||||
} else {
|
||||
enet[0] = 0x02;
|
||||
enet[1] = 0x00;
|
||||
enet[2] = 0x00;
|
||||
enet[3] = 0x00;
|
||||
enet[4] = 0x00;
|
||||
if (1 == sbcommon_get_master() ) {
|
||||
/* Master/Primary card */
|
||||
enet[5] = 0x01;
|
||||
} else {
|
||||
/* Slave/Secondary card */
|
||||
enet [5] = 0x02;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
|
||||
return (ctrlc());
|
||||
}
|
||||
#endif
|
||||
@ -1,60 +0,0 @@
|
||||
#ifndef __SBCOMMON_H__
|
||||
#define __SBCOMMON_H__
|
||||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
|
||||
/*
|
||||
* GPIO Settings
|
||||
*/
|
||||
/* Chassis settings */
|
||||
#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */
|
||||
#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */
|
||||
|
||||
/* Debug LEDs */
|
||||
#define SBCOMMON_GPIO_DBGLED_0 0x00000400
|
||||
#define SBCOMMON_GPIO_DBGLED_1 0x00000200
|
||||
#define SBCOMMON_GPIO_DBGLED_2 0x00100000
|
||||
#define SBCOMMON_GPIO_DBGLED_3 0x00000100
|
||||
|
||||
#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \
|
||||
SBCOMMON_GPIO_DBGLED_1 | \
|
||||
SBCOMMON_GPIO_DBGLED_2 | \
|
||||
SBCOMMON_GPIO_DBGLED_3)
|
||||
|
||||
#define SBCOMMON_GPIO_SYS_FAULT 0x00000080
|
||||
#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040
|
||||
#define SBCOMMON_GPIO_SYS_STATUS 0x00000020
|
||||
|
||||
#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS)
|
||||
|
||||
#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \
|
||||
SBCOMMON_GPIO_DBGLED_1 | \
|
||||
SBCOMMON_GPIO_DBGLED_2 | \
|
||||
SBCOMMON_GPIO_DBGLED_3 | \
|
||||
SBCOMMON_GPIO_SYS_STATUS)
|
||||
|
||||
typedef struct ppc440_gpio_regs {
|
||||
volatile unsigned long out;
|
||||
volatile unsigned long tri_state;
|
||||
volatile unsigned long dummy[4];
|
||||
volatile unsigned long open_drain;
|
||||
volatile unsigned long in;
|
||||
} __attribute__((packed)) ppc440_gpio_regs_t;
|
||||
|
||||
int sbcommon_get_master(void);
|
||||
int sbcommon_secondary_present(void);
|
||||
unsigned short sbcommon_get_serial_number(void);
|
||||
void sbcommon_fans(void);
|
||||
void board_get_enetaddr(int macaddr_idx, uchar *enet);
|
||||
|
||||
#endif /* __SBCOMMON_H__ */
|
||||
@ -1,12 +0,0 @@
|
||||
if TARGET_KAREF
|
||||
|
||||
config SYS_BOARD
|
||||
default "karef"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "sandburst"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "KAREF"
|
||||
|
||||
endif
|
||||
@ -1,6 +0,0 @@
|
||||
KAREF BOARD
|
||||
#M: Travis Sawyer <travis.sawyer@sandburst.com>
|
||||
S: Orphan (since 2014-03)
|
||||
F: board/sandburst/karef/
|
||||
F: include/configs/KAREF.h
|
||||
F: configs/KAREF_defconfig
|
||||
@ -1,16 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2005
|
||||
# Sandburst Corporation
|
||||
# Travis B. Sawyer
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
# TBS: add for debugging purposes
|
||||
ccflags-y += -DBUILDUSER='"$(shell whoami)"'
|
||||
|
||||
obj-y = karef.o ../common/flash.o ../common/sb_common.o
|
||||
extra-y += init.o
|
||||
@ -1,21 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2005
|
||||
# Sandburst Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
#
|
||||
# Sandburst Corporation Metrobox Reference Design
|
||||
# Travis B. Sawyer
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
@ -1,324 +0,0 @@
|
||||
/* ****************************************************************
|
||||
* Common defs for reg spec for chip ka_of
|
||||
* Auto-generated by trex2: DO NOT HAND-EDIT!!
|
||||
* ****************************************************************
|
||||
*/
|
||||
|
||||
#ifndef HAL_KA_OF_AUTO_H
|
||||
#define HAL_KA_OF_AUTO_H
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------
|
||||
* For block: 'ofem'
|
||||
*/
|
||||
|
||||
/* ---- Block instance addressing (for block-select) */
|
||||
#define OFEM_BLOCK_ADDR_BIT_L 6
|
||||
#define OFEM_BLOCK_ADDR_BIT_H 9
|
||||
#define OFEM_BLOCK_ADDR_WIDTH 4
|
||||
|
||||
#define OFEM_ADDR 0x0
|
||||
|
||||
/* ---- Reg addressing (within block) */
|
||||
#define OFEM_REG_ADDR_BIT_L 2
|
||||
#define OFEM_REG_ADDR_BIT_H 5
|
||||
#define OFEM_REG_ADDR_WIDTH 4
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_REVISION */
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_RESET */
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_CNTL */
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_INTERRUPT */
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_INTERRUPT_MASK */
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_SCRATCH */
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_OF_OFEM_SCRATCH_MASK */
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014
|
||||
#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_REVISION */
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_RESET */
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_CNTL */
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_INTERRUPT */
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_INTERRUPT_MASK */
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_SCRATCH */
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_OF_OFEM_SCRATCH_MASK */
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
|
||||
|
||||
#endif /* matches #ifndef HAL_KA_OF_AUTO_H */
|
||||
@ -1,836 +0,0 @@
|
||||
/* ****************************************************************
|
||||
* Common defs for reg spec for chip ka_sc
|
||||
* Auto-generated by trex2: DO NOT HAND-EDIT!!
|
||||
* ****************************************************************
|
||||
*/
|
||||
|
||||
#ifndef HAL_KA_SC_AUTO_H
|
||||
#define HAL_KA_SC_AUTO_H
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------
|
||||
* For block: 'scan'
|
||||
*/
|
||||
|
||||
/* ---- Block instance addressing (for block-select) */
|
||||
#define SCAN_BLOCK_ADDR_BIT_L 7
|
||||
#define SCAN_BLOCK_ADDR_BIT_H 9
|
||||
#define SCAN_BLOCK_ADDR_WIDTH 3
|
||||
|
||||
#define SCAN_ADDR 0x0
|
||||
|
||||
/* ---- Reg addressing (within block) */
|
||||
#define SCAN_REG_ADDR_BIT_L 2
|
||||
#define SCAN_REG_ADDR_BIT_H 6
|
||||
#define SCAN_REG_ADDR_WIDTH 5
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_REVISION */
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_RESET */
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_STATUS */
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_CNTL */
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_BRD_INFO */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_FROM_0 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_FROM_1 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_TO_0 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_TO_1 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCAN_CTRL */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_PLL_CTRL */
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_CORE_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_DR_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SPI_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_BRD_BRD_IN */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_MISC */
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_INTERRUPT */
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_INTERRUPT_MASK */
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCRATCH */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register KA_SC_SCAN_SCRATCH_MASK */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018
|
||||
#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_REVISION */
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_RESET */
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_STATUS */
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_CNTL */
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_BRD_INFO */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_FROM_0 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_FROM_1 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_TO_0 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_TO_1 */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCAN_CTRL */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_PLL_CTRL */
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_CORE_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_DR_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SPI_CLK_COUNT */
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_BRD_BRD_IN */
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_MISC */
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_INTERRUPT */
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_INTERRUPT_MASK */
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCRATCH */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register KA_SC_SCAN_SCRATCH_MASK */
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
|
||||
|
||||
#endif /* matches #ifndef HAL_KA_SC_AUTO_H */
|
||||
@ -1,39 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
/*
|
||||
* Ported from Ebony init.S by Travis B. Sawyer
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
||||
tlbtab_end
|
||||
@ -1,595 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
* Travis B. Sawyer
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "karef.h"
|
||||
#include "karef_version.h"
|
||||
#include <timestamp.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
#include "../common/sb_common.h"
|
||||
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
|
||||
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
|
||||
#include <net.h>
|
||||
#endif
|
||||
|
||||
void fpga_init (void);
|
||||
|
||||
KAREF_BOARD_ID_ST board_id_as[] =
|
||||
{
|
||||
{"Undefined"}, /* Not specified */
|
||||
{"Kamino Reference Design"},
|
||||
{"Reserved"}, /* Reserved for future use */
|
||||
{"Reserved"}, /* Reserved for future use */
|
||||
};
|
||||
|
||||
KAREF_BOARD_ID_ST ofem_board_id_as[] =
|
||||
{
|
||||
{"Undefined"},
|
||||
{"1x10 + 10x2"},
|
||||
{"Reserved"},
|
||||
{"Reserved"},
|
||||
};
|
||||
|
||||
/*************************************************************************
|
||||
* board_early_init_f
|
||||
*
|
||||
* Setup chip selects, initialize the Opto-FPGA, initialize
|
||||
* interrupt polarity and triggers.
|
||||
************************************************************************/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
ppc440_gpio_regs_t *gpio_regs;
|
||||
|
||||
/* Enable GPIO interrupts */
|
||||
mtsdr(SDR0_PFC0, 0x00103E00);
|
||||
|
||||
/* Setup access for LEDs, and system topology info */
|
||||
gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
|
||||
gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
|
||||
gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
|
||||
|
||||
/* Turn on all the leds for now */
|
||||
gpio_regs->out = SBCOMMON_GPIO_LEDS;
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Initialize EBC CONFIG
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(EBC0_CFG,
|
||||
EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
|
||||
EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
|
||||
EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
|
||||
EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
|
||||
EBC_CFG_PR_32);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| 1/2 MB FLASH. Initialize bank 0 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB0AP,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
/*--------------------------------------------------------------------+
|
||||
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB1AP,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Compact Flash, uses 2 Chip Selects (2 & 6)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB2AP,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| KaRef Scan FPGA. Initialize bank 3 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB5AP,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| MAC A & B for Kamino. OFEM FPGA decodes the addresses
|
||||
| Initialize bank 4 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB4AP,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
|
||||
EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| OFEM FPGA Initialize bank 5 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB3AP,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
|
||||
mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Compact Flash, uses 2 Chip Selects (2 & 6)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB6AP,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| BME-32. Initialize bank 7 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB7AP,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
+-------------------------------------------------------------------*/
|
||||
/*
|
||||
* Because of the interrupt handling rework to handle 440GX interrupts
|
||||
* with the common code, we needed to change names of the UIC registers.
|
||||
* Here the new relationship:
|
||||
*
|
||||
* U-Boot name 440GX name
|
||||
* -----------------------
|
||||
* UIC0 UICB0
|
||||
* UIC1 UIC0
|
||||
* UIC2 UIC1
|
||||
* UIC3 UIC2
|
||||
*/
|
||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC1ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC1CR, 0x00000000); /* all non- critical */
|
||||
mtdcr (UIC1PR, 0xfffffe03); /* polarity */
|
||||
mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
|
||||
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC2ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
|
||||
mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
|
||||
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC3ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC3PR, 0xffff83ff); /* polarity */
|
||||
mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
|
||||
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC0SR, 0xfc000000); /* clear all */
|
||||
mtdcr (UIC0ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC0PR, 0xfc000000);
|
||||
mtdcr (UIC0TR, 0x00000000);
|
||||
mtdcr (UIC0VR, 0x00000001);
|
||||
|
||||
fpga_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* checkboard
|
||||
*
|
||||
* Dump pertinent info to the console
|
||||
************************************************************************/
|
||||
int checkboard (void)
|
||||
{
|
||||
sys_info_t sysinfo;
|
||||
unsigned char brd_rev, brd_id;
|
||||
unsigned short sernum;
|
||||
unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
|
||||
unsigned char ofem_brd_rev, ofem_brd_id;
|
||||
KAREF_FPGA_REGS_ST *karef_ps;
|
||||
OFEM_FPGA_REGS_ST *ofem_ps;
|
||||
|
||||
karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
|
||||
ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
|
||||
|
||||
scan_id = (unsigned char)((karef_ps->revision_ul &
|
||||
SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
|
||||
|
||||
scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
|
||||
|
||||
brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
|
||||
|
||||
brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
|
||||
|
||||
ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
|
||||
|
||||
ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
|
||||
|
||||
if (0xF != ofem_brd_id) {
|
||||
ofem_id = (unsigned char)((ofem_ps->revision_ul &
|
||||
SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
|
||||
>> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
|
||||
|
||||
ofem_rev = (unsigned char)((ofem_ps->revision_ul &
|
||||
SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
|
||||
}
|
||||
|
||||
get_sys_info (&sysinfo);
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf ("Board: Sandburst Corporation Kamino Reference Design "
|
||||
"Serial Number: %d\n", sernum);
|
||||
printf ("%s\n", KAREF_U_BOOT_REL_STR);
|
||||
|
||||
printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
|
||||
if (sbcommon_get_master()) {
|
||||
printf("Slot 0 - Master\nSlave board");
|
||||
if (sbcommon_secondary_present())
|
||||
printf(" present\n");
|
||||
else
|
||||
printf(" not detected\n");
|
||||
} else {
|
||||
printf("Slot 1 - Slave\n\n");
|
||||
}
|
||||
|
||||
printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev);
|
||||
printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id);
|
||||
if(0xF != ofem_brd_id) {
|
||||
printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev);
|
||||
printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
|
||||
}
|
||||
|
||||
/* Fix the ack in the bme 32 */
|
||||
udelay(5000);
|
||||
out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
|
||||
asm("eieio");
|
||||
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* misc_init_f
|
||||
*
|
||||
* Initialize I2C bus one to gain access to the fans
|
||||
************************************************************************/
|
||||
int misc_init_f (void)
|
||||
{
|
||||
/* Turn on fans 3 & 4 */
|
||||
sbcommon_fans();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* misc_init_r
|
||||
*
|
||||
* Do nothing.
|
||||
************************************************************************/
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
uchar enetaddr[6];
|
||||
KAREF_FPGA_REGS_ST *karef_ps;
|
||||
OFEM_FPGA_REGS_ST *ofem_ps;
|
||||
|
||||
if(NULL != getenv("secondserial")) {
|
||||
puts("secondserial is set, switching to second serial port\n");
|
||||
setenv("stderr", "serial1");
|
||||
setenv("stdout", "serial1");
|
||||
setenv("stdin", "serial1");
|
||||
}
|
||||
|
||||
setenv("ubrelver", KAREF_U_BOOT_REL_STR);
|
||||
|
||||
memset(envstr, 0, 255);
|
||||
sprintf (envstr, "Built %s %s by %s",
|
||||
U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
|
||||
setenv("bldstr", envstr);
|
||||
saveenv();
|
||||
|
||||
if( getenv("autorecover")) {
|
||||
setenv("autorecover", NULL);
|
||||
saveenv();
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf("\nSetting up environment for automatic filesystem recovery\n");
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
||||
"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
|
||||
sernum, sernum);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
|
||||
"fatload ide 0 8100000 pramdisk;"
|
||||
"bootm 8000000 8100000");
|
||||
|
||||
printf("Done. Please type allow the system to continue to boot\n");
|
||||
}
|
||||
|
||||
if( getenv("fakeled")) {
|
||||
karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
|
||||
ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
|
||||
ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
|
||||
karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
|
||||
setenv("bootdelay", "-1");
|
||||
saveenv();
|
||||
printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HAS_ETH0
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
|
||||
board_get_enetaddr(0, enetaddr);
|
||||
eth_setenv_enetaddr("ethaddr", enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_ETH1
|
||||
if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
|
||||
board_get_enetaddr(1, enetaddr);
|
||||
eth_setenv_enetaddr("eth1addr", enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_ETH2
|
||||
if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
|
||||
board_get_enetaddr(2, enetaddr);
|
||||
eth_setenv_enetaddr("eth2addr", enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_ETH3
|
||||
if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
|
||||
board_get_enetaddr(3, enetaddr);
|
||||
eth_setenv_enetaddr("eth3addr", enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* ide_set_reset
|
||||
************************************************************************/
|
||||
#ifdef CONFIG_IDE_RESET
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
KAREF_FPGA_REGS_ST *karef_ps;
|
||||
/* TODO: ide reset */
|
||||
karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
|
||||
|
||||
if (on) {
|
||||
karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
|
||||
} else {
|
||||
karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
/*************************************************************************
|
||||
* fpga_init
|
||||
************************************************************************/
|
||||
void fpga_init(void)
|
||||
{
|
||||
KAREF_FPGA_REGS_ST *karef_ps;
|
||||
OFEM_FPGA_REGS_ST *ofem_ps;
|
||||
unsigned char ofem_id;
|
||||
unsigned long tmp;
|
||||
|
||||
/* Ensure we have power all around */
|
||||
udelay(500);
|
||||
|
||||
karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
|
||||
tmp =
|
||||
SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
|
||||
SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
|
||||
|
||||
karef_ps->reset_ul = tmp;
|
||||
|
||||
/*
|
||||
* Wait a bit to allow the ofem fpga to get its brains
|
||||
*/
|
||||
udelay(5000);
|
||||
|
||||
/*
|
||||
* Check to see if the ofem is there
|
||||
*/
|
||||
ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
|
||||
>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
|
||||
if(0xF != ofem_id) {
|
||||
tmp =
|
||||
SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
|
||||
SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
|
||||
SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
|
||||
|
||||
ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
|
||||
ofem_ps->reset_ul = tmp;
|
||||
|
||||
ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
|
||||
}
|
||||
|
||||
karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
|
||||
|
||||
asm("eieio");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
memset(envstr, 0, 255);
|
||||
/*
|
||||
* Setup our ip address
|
||||
*/
|
||||
sprintf(envstr, "10.100.70.%d", sernum);
|
||||
|
||||
setenv("ipaddr", envstr);
|
||||
/*
|
||||
* Setup the host ip address
|
||||
*/
|
||||
setenv("serverip", "10.100.17.10");
|
||||
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
|
||||
"rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
|
||||
"nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
|
||||
"255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
|
||||
sernum, sernum, sernum);
|
||||
|
||||
setenv("bootargs_nfs", envstr);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup CF bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
|
||||
"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
|
||||
sernum, sernum);
|
||||
|
||||
setenv("bootargs_cf", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
|
||||
setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
|
||||
|
||||
/*
|
||||
* Setup compact flash boot command
|
||||
*/
|
||||
setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
|
||||
|
||||
saveenv();
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf("\nSetting up environment for filesystem recovery\n");
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
||||
"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
|
||||
sernum, sernum);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
|
||||
setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
|
||||
"fatload ide 0 8100000 pramdisk;"
|
||||
"bootm 8000000 8100000");
|
||||
|
||||
printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
|
||||
" please type fsrecover.sh<cr>\n");
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
|
||||
"Set environment to factory defaults", "");
|
||||
|
||||
U_BOOT_CMD(karecover, 1, 1, karefRecover,
|
||||
"Set environment to allow for fs recovery", "");
|
||||
@ -1,60 +0,0 @@
|
||||
#ifndef __KAREF_H__
|
||||
#define __KAREF_H__
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Sandburst Corporation
|
||||
* Travis B. Sawyer
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/* Ka Reference Design OFEM FPGA Registers & definitions */
|
||||
#include "hal_ka_sc_auto.h"
|
||||
#include "hal_ka_of_auto.h"
|
||||
|
||||
typedef struct karef_board_id_s {
|
||||
const char name[40];
|
||||
} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
|
||||
|
||||
/* SCAN FPGA */
|
||||
typedef struct karef_fpga_regs_s
|
||||
{
|
||||
volatile unsigned long revision_ul; /* Read Only */
|
||||
volatile unsigned long reset_ul; /* Read/Write */
|
||||
volatile unsigned long interrupt_ul; /* Read Only */
|
||||
volatile unsigned long mask_ul; /* Read/Write */
|
||||
volatile unsigned long scratch_ul; /* Read/Write */
|
||||
volatile unsigned long scrmask_ul; /* Read/Write */
|
||||
volatile unsigned long status_ul; /* Read Only */
|
||||
volatile unsigned long control_ul; /* Read/Write */
|
||||
volatile unsigned long boardinfo_ul; /* Read Only */
|
||||
volatile unsigned long scan_from0_ul; /* Read Only */
|
||||
volatile unsigned long scan_from1_ul; /* Read Only */
|
||||
volatile unsigned long scan_to0_ul; /* Read/Write */
|
||||
volatile unsigned long scan_to1_ul; /* Read/Write */
|
||||
volatile unsigned long scan_control_ul; /* Read/Write */
|
||||
volatile unsigned long pll_control_ul; /* Read/Write */
|
||||
volatile unsigned long core_clock_cnt_ul; /* Read/Write */
|
||||
volatile unsigned long dr_clock_cnt_ul; /* Read/Write */
|
||||
volatile unsigned long spi_clock_cnt_ul; /* Read/Write */
|
||||
volatile unsigned long brdout_data_ul; /* Read/Write */
|
||||
volatile unsigned long brdout_enable_ul; /* Read/Write */
|
||||
volatile unsigned long brdin_data_ul; /* Read Only */
|
||||
volatile unsigned long misc_ul; /* Read/Write */
|
||||
} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST;
|
||||
|
||||
/* OFEM FPGA */
|
||||
typedef struct ofem_fpga_regs_s
|
||||
{
|
||||
volatile unsigned long revision_ul; /* Read Only */
|
||||
volatile unsigned long reset_ul; /* Read/Write */
|
||||
volatile unsigned long interrupt_ul; /* Read Only */
|
||||
volatile unsigned long mask_ul; /* Read/Write */
|
||||
volatile unsigned long scratch_ul; /* Read/Write */
|
||||
volatile unsigned long scrmask_ul; /* Read/Write */
|
||||
volatile unsigned long control_ul; /* Read/Write */
|
||||
volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */
|
||||
} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST;
|
||||
|
||||
|
||||
#endif /* __KAREF_H__ */
|
||||
@ -1,10 +0,0 @@
|
||||
#ifndef _KAREF_VERSION_H_
|
||||
#define _KAREF_VERSION_H_
|
||||
/*
|
||||
* Copyright (C) 2005 Sandburst Corporation
|
||||
* Travis B. Sawyer
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#define KAREF_U_BOOT_REL_STR "Release 0.0.7"
|
||||
#endif
|
||||
@ -1,130 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/ppc4xx/start.o (.text)
|
||||
board/sandburst/karef/init.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/traps.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/speed.o (.text)
|
||||
drivers/net/4xx_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
arch/powerpc/lib/extable.o (.text)
|
||||
lib/zlib.o (.text)
|
||||
|
||||
/* common/env_embedded.o(.text) */
|
||||
|
||||
*(.text)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
@ -1,12 +0,0 @@
|
||||
if TARGET_METROBOX
|
||||
|
||||
config SYS_BOARD
|
||||
default "metrobox"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "sandburst"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "METROBOX"
|
||||
|
||||
endif
|
||||
@ -1,6 +0,0 @@
|
||||
METROBOX BOARD
|
||||
#M: Travis Sawyer <travis.sawyer@sandburst.com>
|
||||
S: Orphan (since 2014-03)
|
||||
F: board/sandburst/metrobox/
|
||||
F: include/configs/METROBOX.h
|
||||
F: configs/METROBOX_defconfig
|
||||
@ -1,15 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2005
|
||||
# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
# TBS: add for debugging purposes
|
||||
ccflags-y += -DBUILDUSER='"$(shell whoami)"'
|
||||
|
||||
obj-y = metrobox.o ../common/flash.o ../common/sb_common.o
|
||||
extra-y += init.o
|
||||
@ -1,16 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2005
|
||||
# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
@ -1,553 +0,0 @@
|
||||
/* ****************************************************************
|
||||
* Common defs for reg spec for chip xc
|
||||
* Auto-generated by trex2: DO NOT HAND-EDIT!!
|
||||
* ****************************************************************
|
||||
*/
|
||||
|
||||
#ifndef HAL_XC_AUTO_H
|
||||
#define HAL_XC_AUTO_H
|
||||
|
||||
/* ----------------------------------------------------------------
|
||||
* For block: 'xcvr_cntl'
|
||||
*/
|
||||
|
||||
/* ---- Block instance addressing (for block-select) */
|
||||
#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
|
||||
#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
|
||||
#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4
|
||||
|
||||
#define XCVR_CNTL_ADDR 0x0
|
||||
|
||||
/* ---- Reg addressing (within block) */
|
||||
#define XCVR_CNTL_REG_ADDR_BIT_L 2
|
||||
#define XCVR_CNTL_REG_ADDR_BIT_H 5
|
||||
#define XCVR_CNTL_REG_ADDR_WIDTH 4
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_REVISION */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_RESET */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_STATUS */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_CNTL */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_BRD_INFO */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_INTERRUPT */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_SCRATCH */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018
|
||||
#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000
|
||||
#endif
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_REVISION */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_RESET */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_STATUS */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_CNTL */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_BRD_INFO */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_INTERRUPT */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_SCRATCH */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000
|
||||
|
||||
/* ================================================================
|
||||
* Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
|
||||
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff
|
||||
|
||||
#endif /* matches #ifndef HAL_XC_AUTO_H */
|
||||
@ -1,37 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2005
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
||||
tlbtab_end
|
||||
@ -1,561 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2005
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "metrobox.h"
|
||||
#include "metrobox_version.h"
|
||||
#include <timestamp.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <i2c.h>
|
||||
#include "../common/sb_common.h"
|
||||
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
|
||||
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
|
||||
#include <net.h>
|
||||
#endif
|
||||
|
||||
void fpga_init (void);
|
||||
|
||||
METROBOX_BOARD_ID_ST board_id_as[] =
|
||||
{ {"Undefined"}, /* Not specified */
|
||||
{"2x10Gb"}, /* 2 ports, 10 GbE */
|
||||
{"20x1Gb"}, /* 20 ports, 1 GbE */
|
||||
{"Reserved"}, /* Reserved for future use */
|
||||
};
|
||||
|
||||
/*************************************************************************
|
||||
* board_early_init_f
|
||||
*
|
||||
* Setup chip selects, initialize the Opto-FPGA, initialize
|
||||
* interrupt polarity and triggers.
|
||||
************************************************************************/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
ppc440_gpio_regs_t *gpio_regs;
|
||||
|
||||
/* Enable GPIO interrupts */
|
||||
mtsdr(SDR0_PFC0, 0x00103E00);
|
||||
|
||||
/* Setup access for LEDs, and system topology info */
|
||||
gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
|
||||
gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
|
||||
gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
|
||||
|
||||
/* Turn on all the leds for now */
|
||||
gpio_regs->out = SBCOMMON_GPIO_LEDS;
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Initialize EBC CONFIG
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(EBC0_CFG,
|
||||
EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
|
||||
EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
|
||||
EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
|
||||
EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
|
||||
EBC_CFG_PR_32);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| 1/2 MB FLASH. Initialize bank 0 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB0AP,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
/*--------------------------------------------------------------------+
|
||||
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB1AP,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Compact Flash, uses 2 Chip Selects (2 & 6)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB2AP,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| OPTO & OFEM FPGA. Initialize bank 3 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB3AP,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| MAC A for metrobox
|
||||
| MAC A & B for Kamino. OFEM FPGA decodes the addresses
|
||||
| Initialize bank 4 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB4AP,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Metrobox MAC B Initialize bank 5 with default values.
|
||||
| KA REF FPGA Initialize bank 5 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB5AP,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| Compact Flash, uses 2 Chip Selects (2 & 6)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB6AP,
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
|
||||
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
|
||||
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
|
||||
EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
|
||||
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
|
||||
mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
| BME-32. Initialize bank 7 with default values.
|
||||
+-------------------------------------------------------------------*/
|
||||
mtebc(PB7AP,
|
||||
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
|
||||
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
|
||||
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
|
||||
|
||||
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
+-------------------------------------------------------------------*/
|
||||
/*
|
||||
* Because of the interrupt handling rework to handle 440GX interrupts
|
||||
* with the common code, we needed to change names of the UIC registers.
|
||||
* Here the new relationship:
|
||||
*
|
||||
* U-Boot name 440GX name
|
||||
* -----------------------
|
||||
* UIC0 UICB0
|
||||
* UIC1 UIC0
|
||||
* UIC2 UIC1
|
||||
* UIC3 UIC2
|
||||
*/
|
||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC1ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC1CR, 0x00000000); /* all non- critical */
|
||||
mtdcr (UIC1PR, 0xfffffe03); /* polarity */
|
||||
mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
|
||||
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC2ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
|
||||
mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
|
||||
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC3ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC3PR, 0xffff83ff); /* polarity */
|
||||
mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
|
||||
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC0SR, 0xfc000000); /* clear all */
|
||||
mtdcr (UIC0ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC0PR, 0xfc000000);
|
||||
mtdcr (UIC0TR, 0x00000000);
|
||||
mtdcr (UIC0VR, 0x00000001);
|
||||
|
||||
fpga_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* checkboard
|
||||
*
|
||||
* Dump pertinent info to the console
|
||||
************************************************************************/
|
||||
int checkboard (void)
|
||||
{
|
||||
sys_info_t sysinfo;
|
||||
unsigned char brd_rev, brd_id;
|
||||
unsigned short sernum;
|
||||
unsigned char opto_rev, opto_id;
|
||||
OPTO_FPGA_REGS_ST *opto_ps;
|
||||
|
||||
opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
|
||||
|
||||
opto_rev = (unsigned char)((opto_ps->revision_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
|
||||
|
||||
opto_id = (unsigned char)((opto_ps->revision_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
|
||||
|
||||
brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
|
||||
|
||||
brd_id = (unsigned char)((opto_ps->boardinfo_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
|
||||
|
||||
get_sys_info (&sysinfo);
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
|
||||
printf ("%s\n", METROBOX_U_BOOT_REL_STR);
|
||||
|
||||
printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
|
||||
if (sbcommon_get_master()) {
|
||||
printf("Slot 0 - Master\nSlave board");
|
||||
if (sbcommon_secondary_present())
|
||||
printf(" present\n");
|
||||
else
|
||||
printf(" not detected\n");
|
||||
} else {
|
||||
printf("Slot 1 - Slave\n\n");
|
||||
}
|
||||
|
||||
printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
|
||||
printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
|
||||
|
||||
/* Fix the ack in the bme 32 */
|
||||
udelay(5000);
|
||||
out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
|
||||
asm("eieio");
|
||||
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* misc_init_f
|
||||
*
|
||||
* Initialize I2C bus one to gain access to the fans
|
||||
************************************************************************/
|
||||
int misc_init_f (void)
|
||||
{
|
||||
/* Turn on fans */
|
||||
sbcommon_fans();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* misc_init_r
|
||||
*
|
||||
* Do nothing.
|
||||
************************************************************************/
|
||||
int misc_init_r (void)
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
uchar enetaddr[6];
|
||||
unsigned char opto_rev;
|
||||
OPTO_FPGA_REGS_ST *opto_ps;
|
||||
|
||||
opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
|
||||
|
||||
if(NULL != getenv("secondserial")) {
|
||||
puts("secondserial is set, switching to second serial port\n");
|
||||
setenv("stderr", "serial1");
|
||||
setenv("stdout", "serial1");
|
||||
setenv("stdin", "serial1");
|
||||
}
|
||||
|
||||
setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
|
||||
|
||||
memset(envstr, 0, 255);
|
||||
sprintf (envstr, "Built %s %s by %s",
|
||||
U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
|
||||
setenv("bldstr", envstr);
|
||||
saveenv();
|
||||
|
||||
if( getenv("autorecover")) {
|
||||
setenv("autorecover", NULL);
|
||||
saveenv();
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf("\nSetting up environment for automatic filesystem recovery\n");
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
||||
"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
|
||||
sernum, sernum);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
|
||||
"fatload ide 0 8100000 pramdisk;"
|
||||
"bootm 8000000 8100000");
|
||||
|
||||
printf("Done. Please type allow the system to continue to boot\n");
|
||||
}
|
||||
|
||||
if( getenv("fakeled")) {
|
||||
setenv("bootdelay", "-1");
|
||||
saveenv();
|
||||
printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
|
||||
opto_rev = (unsigned char)((opto_ps->revision_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
|
||||
|
||||
if(0x12 <= opto_rev) {
|
||||
opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HAS_ETH0
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
|
||||
board_get_enetaddr(0, enetaddr);
|
||||
eth_setenv_enetaddr("ethaddr", enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_ETH1
|
||||
if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
|
||||
board_get_enetaddr(1, enetaddr);
|
||||
eth_setenv_enetaddr("eth1addr", enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_ETH2
|
||||
if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
|
||||
board_get_enetaddr(2, enetaddr);
|
||||
eth_setenv_enetaddr("eth2addr", enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_ETH3
|
||||
if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
|
||||
board_get_enetaddr(3, enetaddr);
|
||||
eth_setenv_enetaddr("eth3addr", enetaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* ide_set_reset
|
||||
************************************************************************/
|
||||
#ifdef CONFIG_IDE_RESET
|
||||
void ide_set_reset(int on)
|
||||
{
|
||||
OPTO_FPGA_REGS_ST *opto_ps;
|
||||
opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
|
||||
|
||||
if (on) { /* assert RESET */
|
||||
opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
|
||||
} else { /* release RESET */
|
||||
opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
/*************************************************************************
|
||||
* fpga_init
|
||||
************************************************************************/
|
||||
void fpga_init(void)
|
||||
{
|
||||
OPTO_FPGA_REGS_ST *opto_ps;
|
||||
unsigned char opto_rev;
|
||||
unsigned long tmp;
|
||||
|
||||
/* Ensure we have power all around */
|
||||
udelay(500);
|
||||
|
||||
/*
|
||||
* Take appropriate hw bits out of reset
|
||||
*/
|
||||
opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
|
||||
|
||||
tmp =
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
|
||||
SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
|
||||
opto_ps->reset_ul = tmp;
|
||||
/*
|
||||
* Turn on the 'Slow Blink' for the System Error Led.
|
||||
* Ensure FPGA rev is up to at least rev 0x12
|
||||
*/
|
||||
opto_rev = (unsigned char)((opto_ps->revision_ul &
|
||||
SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
|
||||
>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
|
||||
if(0x12 <= opto_rev) {
|
||||
opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
|
||||
}
|
||||
|
||||
asm("eieio");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
memset(envstr, 0, 255);
|
||||
/*
|
||||
* Setup our ip address
|
||||
*/
|
||||
sprintf(envstr, "10.100.60.%d", sernum);
|
||||
|
||||
setenv("ipaddr", envstr);
|
||||
/*
|
||||
* Setup the host ip address
|
||||
*/
|
||||
setenv("serverip", "10.100.17.10");
|
||||
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
|
||||
"rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
|
||||
"nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
|
||||
":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
|
||||
sernum, sernum, sernum);
|
||||
|
||||
setenv("bootargs_nfs", envstr);
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup CF bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
|
||||
"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
|
||||
sernum, sernum);
|
||||
|
||||
setenv("bootargs_cf", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
|
||||
setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
|
||||
|
||||
/*
|
||||
* Setup compact flash boot command
|
||||
*/
|
||||
setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
|
||||
|
||||
saveenv();
|
||||
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned short sernum;
|
||||
char envstr[255];
|
||||
|
||||
sernum = sbcommon_get_serial_number();
|
||||
|
||||
printf("\nSetting up environment for filesystem recovery\n");
|
||||
/*
|
||||
* Setup default bootargs
|
||||
*/
|
||||
memset(envstr, 0, 255);
|
||||
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
||||
"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
|
||||
sernum, sernum);
|
||||
|
||||
setenv("bootargs", envstr);
|
||||
|
||||
/*
|
||||
* Setup Default boot command
|
||||
*/
|
||||
setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
|
||||
"fatload ide 0 8100000 pramdisk;"
|
||||
"bootm 8000000 8100000");
|
||||
|
||||
printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
|
||||
" please type fsrecover.sh<cr>\n");
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
|
||||
"Set environment to factory defaults", "");
|
||||
|
||||
U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
|
||||
"Set environment to allow for fs recovery", "");
|
||||
@ -1,29 +0,0 @@
|
||||
#ifndef __METROBOX_H__
|
||||
#define __METROBOX_H__
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
typedef struct metrobox_board_id_s {
|
||||
const char name[40];
|
||||
} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST;
|
||||
|
||||
|
||||
/* Metrobox Opto-FPGA registers and definitions */
|
||||
#include "hal_xc_auto.h"
|
||||
typedef struct opto_fpga_regs_s {
|
||||
volatile unsigned long revision_ul; /* Read Only */
|
||||
volatile unsigned long reset_ul; /* Read/Write */
|
||||
volatile unsigned long status_ul; /* Read Only */
|
||||
volatile unsigned long interrupt_ul; /* Read Only */
|
||||
volatile unsigned long mask_ul; /* Read/Write */
|
||||
volatile unsigned long scratch_ul; /* Read/Write */
|
||||
volatile unsigned long scrmask_ul; /* Read/Write */
|
||||
volatile unsigned long control_ul; /* Read/Write */
|
||||
volatile unsigned long boardinfo_ul; /* Read Only */
|
||||
} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST;
|
||||
|
||||
#endif /* __METROBOX_H__ */
|
||||
@ -1,11 +0,0 @@
|
||||
#ifndef _METROBOX_VERSION_H_
|
||||
#define _METROBOX_VERSION_H_
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#define METROBOX_U_BOOT_REL_STR "Release 2.0.3"
|
||||
|
||||
#endif
|
||||
@ -1,130 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/ppc4xx/start.o (.text)
|
||||
board/sandburst/metrobox/init.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/traps.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
|
||||
arch/powerpc/cpu/ppc4xx/speed.o (.text)
|
||||
drivers/net/4xx_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
arch/powerpc/lib/extable.o (.text)
|
||||
lib/zlib.o (.text)
|
||||
|
||||
/* common/env_embedded.o(.text) */
|
||||
|
||||
*(.text)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
@ -1,3 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_KAREF=y
|
||||
@ -1,3 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_METROBOX=y
|
||||
@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
|
||||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
KAREF powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
|
||||
METROBOX powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com>
|
||||
PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
|
||||
PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com>
|
||||
flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári Davíðsson <kd@flaga.is>
|
||||
|
||||
@ -1,284 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2004 Sandburst Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
|
||||
* design.
|
||||
***********************************************************************/
|
||||
|
||||
/*
|
||||
* $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
|
||||
|
||||
#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM 1
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
|
||||
#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
|
||||
#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
|
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
|
||||
#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
|
||||
#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
|
||||
#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
|
||||
#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
|
||||
|
||||
/* Here for completeness */
|
||||
#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC
|
||||
*
|
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
|
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base
|
||||
* address for the RTC registers is:
|
||||
*
|
||||
* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
|
||||
*
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
|
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
|
||||
#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_PPC4XX
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH1
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
|
||||
#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
|
||||
#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
|
||||
|
||||
#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Networking
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
|
||||
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
|
||||
#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
|
||||
#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
|
||||
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
|
||||
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
#define CONFIG_NETMASK 255.255.0.0
|
||||
#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
|
||||
#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_BEDBUG
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
|
||||
/* Include NetConsole support */
|
||||
#define CONFIG_NETCONSOLE
|
||||
|
||||
/* Include auto complete with tabs */
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Console Buffer
|
||||
*----------------------------------------------------------------------*/
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory Test
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Compact Flash (in true IDE mode)
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
|
||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
|
||||
|
||||
#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
|
||||
to get to the correct offset */
|
||||
#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI
|
||||
*----------------------------------------------------------------------*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
|
||||
#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -1,349 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2004 Sandburst Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* METROBOX.h - configuration Sandburst MetroBox
|
||||
***********************************************************************/
|
||||
|
||||
/*
|
||||
* $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
|
||||
*
|
||||
*
|
||||
* $Log: METROBOX.h,v $
|
||||
* Revision 1.21 2005/06/03 15:05:25 tsawyer
|
||||
* MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
|
||||
*
|
||||
* Revision 1.20 2005/04/11 20:51:11 tsawyer
|
||||
* fix ethernet
|
||||
*
|
||||
* Revision 1.19 2005/04/06 15:13:36 tsawyer
|
||||
* Update appropriate files to coincide with u-boot 1.1.3
|
||||
*
|
||||
* Revision 1.18 2005/03/10 14:16:02 tsawyer
|
||||
* add def'n for cis8201 short etch option.
|
||||
*
|
||||
* Revision 1.17 2005/03/09 19:49:51 tsawyer
|
||||
* Remove KGDB to allow use of 2nd serial port
|
||||
*
|
||||
* Revision 1.16 2004/12/02 19:00:23 tsawyer
|
||||
* Add misc_init_f to turn on i2c-1 and all four fans before sdram init
|
||||
*
|
||||
* Revision 1.15 2004/09/15 18:04:12 tsawyer
|
||||
* add multiple serial port support
|
||||
*
|
||||
* Revision 1.14 2004/09/03 15:27:51 tsawyer
|
||||
* All metrobox boards are at 66.66 sys clock
|
||||
*
|
||||
* Revision 1.13 2004/08/05 20:27:46 tsawyer
|
||||
* Remove system ace definitions, add net console support
|
||||
*
|
||||
* Revision 1.12 2004/07/29 20:00:13 tsawyer
|
||||
* Add i2c bus 1
|
||||
*
|
||||
* Revision 1.11 2004/07/21 13:44:18 tsawyer
|
||||
* SystemACE is out, CF direct to local bus is in
|
||||
*
|
||||
* Revision 1.10 2004/06/29 19:08:55 tsawyer
|
||||
* Add CONFIG_MISC_INIT_R
|
||||
*
|
||||
* Revision 1.9 2004/06/28 21:30:53 tsawyer
|
||||
* Fix default BOOTARGS
|
||||
*
|
||||
* Revision 1.8 2004/06/17 15:51:08 tsawyer
|
||||
* auto complete
|
||||
*
|
||||
* Revision 1.7 2004/06/17 15:08:49 tsawyer
|
||||
* Add autocomplete
|
||||
*
|
||||
* Revision 1.6 2004/06/15 12:33:57 tsawyer
|
||||
* debugging checkpoint
|
||||
*
|
||||
* Revision 1.5 2004/06/12 19:48:28 tsawyer
|
||||
* Debugging checkpoint
|
||||
*
|
||||
* Revision 1.4 2004/06/02 13:03:06 tsawyer
|
||||
* Fix eth addrs
|
||||
*
|
||||
* Revision 1.3 2004/05/18 19:56:10 tsawyer
|
||||
* Change default bootcommand to pImage.metrobox
|
||||
*
|
||||
* Revision 1.2 2004/05/18 14:13:44 tsawyer
|
||||
* Add bringup values for bootargs and bootcommand.
|
||||
* Remove definition of ipaddress and serverip addresses.
|
||||
*
|
||||
* Revision 1.1 2004/04/16 15:08:54 tsawyer
|
||||
* Initial Revision
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_METROBOX 1 /* Board is Metrobox */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
|
||||
|
||||
#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM 1
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
|
||||
#define CONFIG_IDENT_STRING " Sandburst Metrobox"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
|
||||
#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
|
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
|
||||
#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
|
||||
#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
|
||||
#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC
|
||||
*
|
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
|
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base
|
||||
* address for the RTC registers is:
|
||||
*
|
||||
* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
|
||||
*
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
|
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
|
||||
#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_PPC4XX
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH1
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
|
||||
#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
|
||||
#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
|
||||
|
||||
#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
|
||||
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
|
||||
#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000"
|
||||
#define CONFIG_BOOTDELAY 5 /* disable autoboot */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Networking
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
|
||||
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
|
||||
#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
|
||||
#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
|
||||
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
|
||||
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
#define CONFIG_NETMASK 255.255.0.0
|
||||
#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
|
||||
#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_BEDBUG
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
|
||||
/* Include NetConsole support */
|
||||
#define CONFIG_NETCONSOLE
|
||||
|
||||
/* Include auto complete with tabs */
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "MetroBox=> " /* Monitor Command Prompt */
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Console Buffer
|
||||
*----------------------------------------------------------------------*/
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory Test
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Compact Flash (in true IDE mode)
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
|
||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
|
||||
|
||||
#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
|
||||
to get to the correct offset */
|
||||
#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI
|
||||
*----------------------------------------------------------------------*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
|
||||
#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user