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ppc4xx: Add PPC405EX support

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-10-05 17:10:59 +02:00
parent 1d7b874e9c
commit dbbd125721
21 changed files with 1205 additions and 145 deletions
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6
common/serial.c
View File

@ -41,7 +41,8 @@ struct serial_device *default_serial_console (void)
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
|| defined(CONFIG_MPC5xxx)
#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
@ -91,7 +92,8 @@ void serial_initialize (void)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
|| defined(CONFIG_MPC5xxx)
serial_register(&serial0_device);
serial_register(&serial1_device);
#endif

113
cpu/ppc4xx/4xx_enet.c
View File

@ -133,13 +133,15 @@
#define BI_PHYMODE_GMII 3
#define BI_PHYMODE_RTBI 4
#define BI_PHYMODE_TBI 5
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define BI_PHYMODE_SMII 6
#define BI_PHYMODE_MII 7
#endif
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GRX) || defined(CONFIG_440SP)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
@ -172,6 +174,12 @@ struct eth_device *emac0_dev = NULL;
#define CONFIG_EMAC_NR_START 0
#endif
#if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
#else
#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
#endif
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
@ -197,7 +205,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
{
EMAC_4XX_HW_PST hw_p = dev->priv;
uint32_t failsafe = 10000;
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
unsigned long mfr;
#endif
@ -221,7 +231,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
}
/* EMAC RESET */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
@ -230,7 +242,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
@ -389,6 +403,38 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
}
#endif /* CONFIG_440EPX */
#if defined(CONFIG_405EX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
u32 gmiifer = 0;
/*
* Right now only 2*RGMII is supported. Please extend when needed.
* sr - 2007-09-19
*/
switch (1) {
case 1:
/* 2 x RGMII ports */
out32 (RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
case 2:
/* 2 x SMII ports */
break;
default:
break;
}
/* Ensure we setup mdio for this devnum and ONLY this devnum */
gmiifer = in32(RGMII_FER);
gmiifer |= (1 << (19-devnum));
out32 (RGMII_FER, gmiifer);
return ((int)0x0);
}
#endif /* CONFIG_405EX */
static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
{
int i, j;
@ -402,19 +448,21 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
unsigned short reg_short;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
sys_info_t sysinfo;
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
int ethgroup = -1;
#endif
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
unsigned long mfr;
#endif
EMAC_4XX_HW_PST hw_p = dev->priv;
/* before doing anything, figure out if we have a MAC address */
@ -426,7 +474,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
#endif
@ -498,12 +547,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
#if defined(CONFIG_405EX)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
#endif
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
@ -521,8 +574,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (failsafe <= 0)
printf("\nProblem resetting EMAC!\n");
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
@ -531,7 +585,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
@ -591,7 +646,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
#if defined(CONFIG_CIS8201_PHY)
/*
@ -723,7 +779,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
}
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
if (speed == 1000)
reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
else if (speed == 100)
@ -740,7 +797,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* set the Mal configuration reg */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
@ -978,8 +1036,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/*
* Connect interrupt service routines
*/
irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
(interrupt_handler_t *) enetInt, dev);
}
mtmsr (msr); /* enable interrupts again */
@ -1059,7 +1117,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
}
#if defined (CONFIG_440)
#if defined (CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/*
@ -1073,7 +1131,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
#define UIC0SR uic0sr
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define UICMSR_ETHX uic0msr
#define UICSR_ETHX uic0sr
#else
@ -1601,7 +1660,11 @@ int ppc_4xx_eth_initialize (bd_t * bis)
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[2] = 2;
bis->bi_phymode[3] = 2;
#endif
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
ppc_4xx_eth_setup_bridge(0, bis);
#endif
@ -1649,7 +1712,9 @@ int ppc_4xx_eth_initialize (bd_t * bis)
if (0 == virgin) {
/* set the MAL IER ??? names may change with new spec ??? */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
mal_ier =
MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;

2
cpu/ppc4xx/Makefile
View File

@ -30,7 +30,7 @@ SOBJS = dcr.o
COBJS = 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o \
4xx_pci.o 4xx_pcie.o 4xx_enet.o \
bedbug_405.o commproc.o \
cpu.o cpu_init.o gpio.o i2c.o interrupts.o \
cpu.o cpu_init.o fdt.o gpio.o i2c.o interrupts.o \
miiphy.o ndfc.o sdram.o serial.o speed.o \
tlb.o traps.o usb_ohci.o usb.o usbdev.o

63
cpu/ppc4xx/cpu.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2006
* (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -45,15 +45,6 @@ DECLARE_GLOBAL_DATA_PTR;
void board_reset(void);
#endif
#if defined(CONFIG_440)
#define FREQ_EBC (sys_info.freqEPB)
#elif defined(CONFIG_405EZ)
#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
sys_info.pllExtBusDiv)
#else
#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif
#if defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@ -76,7 +67,8 @@ int pci_async_enabled(void)
}
#endif
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
!defined(CONFIG_405) && !defined(CONFIG_405EX)
int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
@ -110,7 +102,8 @@ int pci_arbiter_enabled(void)
#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
#define I2C_BOOTROM
@ -207,6 +200,21 @@ static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
#endif
#if defined(CONFIG_405EX)
#define SDR0_PINSTP_SHIFT 29
static char *bootstrap_str[] = {
"EBC (8 bits)",
"EBC (16 bits)",
"EBC (16 bits)",
"NAND (8 bits)",
"NAND (8 bits)",
"I2C (Addr 0x54)",
"EBC (8 bits)",
"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
{
@ -241,7 +249,8 @@ int checkcpu (void)
puts("AMCC PowerPC 4");
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ)
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX)
puts("05");
#endif
#if defined(CONFIG_440)
@ -293,6 +302,26 @@ int checkcpu (void)
puts("EZ Rev. A");
break;
case PVR_405EX1_RA:
puts("EX Rev. A");
strcpy(addstr, "Security support");
break;
case PVR_405EX2_RA:
puts("EX Rev. A");
strcpy(addstr, "No Security support");
break;
case PVR_405EXR1_RA:
puts("EXr Rev. A");
strcpy(addstr, "Security support");
break;
case PVR_405EXR2_RA:
puts("EXr Rev. A");
strcpy(addstr, "No Security support");
break;
#if defined(CONFIG_440)
case PVR_440GP_RB:
puts("GP Rev. B");
@ -424,7 +453,7 @@ int checkcpu (void)
printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
sys_info.freqPLB / 1000000,
get_OPB_freq() / 1000000,
FREQ_EBC / 1000000);
sys_info.freqEBC / 1000000);
if (addstr[0] != 0)
printf(" %s\n", addstr);
@ -437,7 +466,7 @@ int checkcpu (void)
printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
#endif /* SDR0_PINSTP_SHIFT */
#if defined(CONFIG_PCI)
#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif
@ -450,11 +479,11 @@ int checkcpu (void)
}
#endif
#if defined(CONFIG_PCI)
#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
putc('\n');
#endif
#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
printf (" 16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
printf (" 32 kB I-Cache 32 kB D-Cache");

14
cpu/ppc4xx/cpu_init.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2006
* (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -112,7 +112,7 @@ cpu_init_f (void)
unsigned long val;
#endif
#if defined(CONFIG_405EP)
#if defined(CONFIG_405EP) || defined (CONFIG_405EX)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
@ -128,13 +128,21 @@ cpu_init_f (void)
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
#if defined(CFG_GPIO0_ISR2H)
out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
#endif
#if defined (CFG_GPIO0_TCR)
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
#endif
#if defined (CONFIG_450EP)
/*
* Set EMAC noise filter bits
*/
mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
#endif /* CONFIG_405EP */
#endif /* CONFIG_405EP */
#if defined(CFG_440_GPIO_TABLE)
gpio_set_chip_configuration();
@ -146,7 +154,7 @@ cpu_init_f (void)
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405))
defined(CONFIG_405EX) || defined(CONFIG_405))
/*
* Move the next instructions into icache, since these modify the flash
* we are running from!

20
cpu/ppc4xx/interrupts.c
View File

@ -52,7 +52,7 @@ struct irq_action {
static struct irq_action irq_vecs[32];
void uic0_interrupt( void * parms); /* UIC0 handler */
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
static struct irq_action irq_vecs1[32]; /* For UIC1 */
void uic1_interrupt( void * parms); /* UIC1 handler */
@ -116,7 +116,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
irq_vecs[vec].count = 0;
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
@ -172,7 +172,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
*/
set_evpr(0x00000000);
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if !defined(CONFIG_440GX)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
@ -378,7 +378,7 @@ void uic0_interrupt( void * parms)
#endif /* CONFIG_440GX */
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
/* Handler for UIC1 interrupt */
void uic1_interrupt( void * parms)
{
@ -525,7 +525,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
struct irq_action *irqa = irq_vecs;
int i = vec;
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64)) {
@ -553,7 +553,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
irqa[i].handler = handler;
irqa[i].arg = arg;
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64))
@ -577,7 +577,7 @@ void irq_free_handler (int vec)
struct irq_action *irqa = irq_vecs;
int i = vec;
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64)) {
@ -599,7 +599,7 @@ void irq_free_handler (int vec)
vec, irq_vecs[vec].handler);
#endif
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64))
@ -641,7 +641,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int vec;
printf ("\nInterrupt-Information:\n");
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
printf ("\nUIC 0\n");
#endif
printf ("Nr Routine Arg Count\n");
@ -656,7 +656,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
}
#if defined(CONFIG_440)
#if defined(CONFIG_440) || defined(CONFIG_405EX)
printf ("\nUIC 1\n");
printf ("Nr Routine Arg Count\n");

22
cpu/ppc4xx/miiphy.c
View File

@ -141,6 +141,16 @@ unsigned int miiphy_getemac_offset (void)
return (eoffset);
#else
#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX)
unsigned long rgmii;
int devnum = 1;
rgmii = in32(RGMII_FER);
if (rgmii & (1 << (19 - devnum)))
return 0x100;
#endif
return 0;
#endif
}
@ -174,7 +184,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
#else
@ -186,7 +197,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
!defined(CONFIG_405EX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
@ -248,7 +260,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
#else
@ -260,7 +273,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
!defined(CONFIG_405EX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */

3
cpu/ppc4xx/ndfc.c
View File

@ -34,7 +34,7 @@
#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
(defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EZ))
defined(CONFIG_405EZ) || defined(CONFIG_405EX))
#include <nand.h>
#include <linux/mtd/ndfc.h>
@ -222,6 +222,7 @@ int board_nand_init(struct nand_chip *nand)
*/
board_nand_select_device(nand, cs);
out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);
return 0;
}

42
cpu/ppc4xx/serial.c
View File

@ -266,7 +266,7 @@ int serial_tstc ()
/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_440)
defined(CONFIG_405EX) || defined(CONFIG_440)
#if defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@ -318,6 +318,15 @@ int serial_tstc ()
#define UCR0_UDIV_POS 0
#define UCR1_UDIV_POS 8
#define UDIV_MAX 127
#elif defined(CONFIG_405EX)
#define UART0_BASE 0xef600200
#define UART1_BASE 0xef600300
#define CR0_MASK 0x000000ff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#else /* CONFIG_405GP || CONFIG_405CR */
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
@ -391,7 +400,8 @@ typedef struct {
volatile static serial_buffer_t buf_info;
#endif
#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
!defined(CFG_EXT_SERIAL_CLOCK)
static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned short *pbdiv)
{
@ -572,7 +582,31 @@ int serial_init (void)
unsigned short bdiv;
volatile char val;
#if defined(CONFIG_405EZ)
#ifdef CONFIG_405EX
clk = tmp = 0;
mfsdr(UART0_SDR, reg);
reg &= ~CR0_MASK;
#ifdef CFG_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
serial_divs(gd->baudrate, &udiv, &bdiv);
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
/*
* Configure input clock to baudrate generator for all
* available serial ports here
*/
mtsdr(UART0_SDR, reg);
#if defined(UART1_SDR)
mtsdr(UART1_SDR, reg);
#endif
#elif defined(CONFIG_405EZ)
serial_divs(gd->baudrate, &udiv, &bdiv);
clk = tmp = reg = 0;
#else
@ -608,7 +642,7 @@ int serial_init (void)
#endif /* CONFIG_405EP */
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
#endif /* CONFIG_405EZ */
#endif /* CONFIG_405EX */
out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */

180
cpu/ppc4xx/speed.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000
* (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -263,7 +263,7 @@ void get_sys_info (sys_info_t *sysInfo)
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
sysInfo->freqEBC = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv;
/* Figure which timer source to use */
@ -317,7 +317,7 @@ void get_sys_info (sys_info_t * sysInfo)
if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
sysInfo->freqPLB >>= 1;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
}
#else
@ -393,7 +393,7 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
#if defined(CONFIG_YUCCA)
/* Determine PCI Clock Period */
@ -733,6 +733,8 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
* Determine PLB clock frequency
*/
sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv;
}
@ -856,6 +858,9 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
*/
sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) /
sysInfo->pllFwdDiv / sysInfo->pllPlbDiv;
sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) /
sysInfo->pllExtBusDiv;
}
/********************************************
@ -874,13 +879,175 @@ ulong get_OPB_freq (void)
return val;
}
#elif defined(CONFIG_405EX)
/*
* TODO: We need to get the CPR registers and calculate these values correctly!!!!
* We need the specs!!!!
*/
static unsigned char get_fbdv(unsigned char index)
{
unsigned char ret = 0;
/* This is table should be 256 bytes.
* Only take first 52 values.
*/
unsigned char fbdv_tb[] = {
0x00, 0xff, 0x7f, 0xfd,
0x7a, 0xf5, 0x6a, 0xd5,
0x2a, 0xd4, 0x29, 0xd3,
0x26, 0xcc, 0x19, 0xb3,
0x67, 0xce, 0x1d, 0xbb,
0x77, 0xee, 0x5d, 0xba,
0x74, 0xe9, 0x52, 0xa5,
0x4b, 0x96, 0x2c, 0xd8,
0x31, 0xe3, 0x46, 0x8d,
0x1b, 0xb7, 0x6f, 0xde,
0x3d, 0xfb, 0x76, 0xed,
0x5a, 0xb5, 0x6b, 0xd6,
0x2d, 0xdb, 0x36, 0xec,
};
if ((index & 0x7f) == 0)
return 1;
while (ret < sizeof (fbdv_tb)) {
if (fbdv_tb[ret] == index)
break;
ret++;
}
ret++;
return ret;
}
#define PLL_FBK_PLL_LOCAL 0
#define PLL_FBK_CPU 1
#define PLL_FBK_PERCLK 5
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
unsigned long m = 1;
unsigned int tmp;
unsigned char fwdva[16] = {
1, 2, 14, 9, 4, 11, 16, 13,
12, 5, 6, 15, 10, 7, 8, 3,
};
unsigned char sel, cpudv0, plb2xDiv;
mfcpr(cpr0_plld, tmp);
/*
* Determine forward divider A
*/
sysInfo->pllFwdDiv = fwdva[((tmp >> 16) & 0x0f)]; /* FWDVA */
/*
* Determine FBK_DIV.
*/
sysInfo->pllFbkDiv = get_fbdv(((tmp >> 24) & 0x0ff)); /* FBDV */
/*
* Determine PLBDV0
*/
sysInfo->pllPlbDiv = 2;
/*
* Determine PERDV0
*/
mfcpr(cpr0_perd, tmp);
tmp = (tmp >> 24) & 0x03;
sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp;
/*
* Determine OPBDV0
*/
mfcpr(cpr0_opbd, tmp);
tmp = (tmp >> 24) & 0x03;
sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
/* Determine PLB2XDV0 */
mfcpr(cpr0_plbd, tmp);
tmp = (tmp >> 16) & 0x07;
plb2xDiv = (tmp == 0) ? 8 : tmp;
/* Determine CPUDV0 */
mfcpr(cpr0_cpud, tmp);
tmp = (tmp >> 24) & 0x07;
cpudv0 = (tmp == 0) ? 8 : tmp;
/* Determine SEL(5:7) in CPR0_PLLC */
mfcpr(cpr0_pllc, tmp);
sel = (tmp >> 24) & 0x07;
/*
* Determine the M factor
* PLL local: M = FBDV
* CPU clock: M = FBDV * FWDVA * CPUDV0
* PerClk : M = FBDV * FWDVA * PLB2XDV0 * PLBDV0(2) * OPBDV0 * PERDV0
*
*/
switch (sel) {
case PLL_FBK_CPU:
m = sysInfo->pllFwdDiv * cpudv0;
break;
case PLL_FBK_PERCLK:
m = sysInfo->pllFwdDiv * plb2xDiv * 2
* sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv;
break;
case PLL_FBK_PLL_LOCAL:
break;
default:
printf("%s unknown m\n", __FUNCTION__);
return;
}
m *= sysInfo->pllFbkDiv;
/*
* Determine VCO clock frequency
*/
sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
(unsigned long long)sysClkPeriodPs;
/*
* Determine CPU clock frequency
*/
sysInfo->freqProcessor = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * cpudv0);
/*
* Determine PLB clock frequency, ddr1x should be the same
*/
sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * plb2xDiv * 2);
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqDDR = sysInfo->freqPLB;
sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
}
/********************************************
* get_OPB_freq
* return OPB bus freq in Hz
*********************************************/
ulong get_OPB_freq (void)
{
ulong val = 0;
PPC405_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllOpbDiv;
return val;
}
#endif
int get_clocks (void)
{
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_440) || defined(CONFIG_405)
defined(CONFIG_405EX) || defined(CONFIG_405) || \
defined(CONFIG_440)
sys_info_t sys_info;
get_sys_info (&sys_info);
@ -907,7 +1074,8 @@ ulong get_bus_freq (ulong dummy)
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_440) || defined(CONFIG_405)
defined(CONFIG_405EX) || defined(CONFIG_405) || \
defined(CONFIG_440)
sys_info_t sys_info;
get_sys_info (&sys_info);

69
cpu/ppc4xx/start.S
View File

@ -800,7 +800,7 @@ _start:
/*----------------------------------------------------------------------- */
/* Enable two 128MB cachable regions. */
/*----------------------------------------------------------------------- */
addis r1,r0,0x8000
addis r1,r0,0xc000
addi r1,r1,0x0001
mticcr r1 /* instruction cache */
@ -823,12 +823,23 @@ _start:
/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405)
defined(CONFIG_405EX) || defined(CONFIG_405)
/*----------------------------------------------------------------------- */
/* Clear and set up some registers. */
/*----------------------------------------------------------------------- */
addi r4,r0,0x0000
#if !defined(CONFIG_405EX)
mtspr sgr,r4
#else
/*
* On 405EX, completely clearing the SGR leads to PPC hangup
* upon PCIe configuration access. The PCIe memory regions
* need to be guarded!
*/
lis r3,0x0000
ori r3,r3,0x7FFC
mtspr sgr,r3
#endif
mtspr dcwr,r4
mtesr r4 /* clear Exception Syndrome Reg */
mttcr r4 /* clear Timer Control Reg */
@ -851,7 +862,7 @@ _start:
/*----------------------------------------------------------------------- */
/* Enable two 128MB cachable regions. */
/*----------------------------------------------------------------------- */
lis r4,0x8000
lis r4,0xc000
ori r4,r4,0x0001
mticcr r4 /* instruction cache */
isync
@ -860,12 +871,34 @@ _start:
ori r4,r4,0x0000
mtdccr r4 /* data cache */
#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
/*----------------------------------------------------------------------- */
/* Tune the speed and size for flash CS0 */
/*----------------------------------------------------------------------- */
bl ext_bus_cntlr_init
#endif
#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
/*
* Boards like the Kilauea (405EX) don't have OCM and can't use
* DCache for init-ram. So setup stack here directly after the
* SDRAM is initialized.
*/
lis r1, CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
/*
* Set up a dummy frame to store reset vector as return address.
* this causes stack underflow to reset board.
*/
stwu r1, -8(r1) /* Save back chain and move SP */
lis r0, RESET_VECTOR@h /* Address of reset vector */
ori r0, r0, RESET_VECTOR@l
stwu r1, -8(r1) /* Save back chain and move SP */
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
#if defined(CONFIG_405EP)
/*----------------------------------------------------------------------- */
@ -983,7 +1016,7 @@ start_ram:
ori r4,r4,0xa000
mtdcr ebccfgd,r4
/* turn on data chache for this region */
/* turn on data cache for this region */
lis r4,0x0080
mtdccr r4
@ -1049,30 +1082,6 @@ start_ram:
/*----------------------------------------------------------------------- */
bl sdram_init
/*
* Setup temporary stack pointer only for boards
* that do not use SDRAM SPD I2C stuff since it
* is already initialized to use DCACHE or OCM
* stacks.
*/
#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
lis r1, CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
/*
* Set up a dummy frame to store reset vector as return address.
* this causes stack underflow to reset board.
*/
stwu r1, -8(r1) /* Save back chain and move SP */
lis r0, RESET_VECTOR@h /* Address of reset vector */
ori r0, r0, RESET_VECTOR@l
stwu r1, -8(r1) /* Save back chain and move SP */
stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
#ifdef CONFIG_NAND_SPL
bl nand_boot /* will not return */
#else
@ -1273,7 +1282,7 @@ icache_enable:
bl invalidate_icache
mtlr r8
isync
addis r3,r0, 0x8000 /* set bit 0 */
addis r3,r0, 0xc000 /* set bit 0 */
mticcr r3
blr

104
cpu/ppc4xx/vecnum.h
View File

@ -270,6 +270,110 @@
#define VECNUM_EIR3 30 /* External interrupt 3 */
#define VECNUM_EIR4 31 /* External interrupt 4 */
#elif defined(CONFIG_405EX)
/* UIC 0 */
#define VECNUM_U0 00
#define VECNUM_U1 01
#define VECNUM_IIC0 02
#define VECNUM_PKA 03
#define VECNUM_TRNG 04
#define VECNUM_EBM 05
#define VECNUM_BGI 06
#define VECNUM_IIC1 07
#define VECNUM_SPI 08
#define VECNUM_EIR0 09
#define VECNUM_MTE 10 /* MAL Tx EOB */
#define VECNUM_MRE 11 /* MAL Rx EOB */
#define VECNUM_DMA0 12
#define VECNUM_DMA1 13
#define VECNUM_DMA2 14
#define VECNUM_DMA3 15
#define VECNUM_PCIE0AL 16
#define VECNUM_PCIE0VPD 17
#define VECNUM_RPCIE0HRST 18
#define VECNUM_FPCIE0HRST 19
#define VECNUM_PCIE0TCR 20
#define VECNUM_PCIEMSI0 21
#define VECNUM_PCIEMSI1 22
#define VECNUM_SECURITY 23
#define VECNUM_ETH0 24
#define VECNUM_ETH1 25
#define VECNUM_PCIEMSI2 26
#define VECNUM_EIR4 27
#define VECNUM_UIC2NC 28
#define VECNUM_UIC2C 29
#define VECNUM_UIC1NC 30
#define VECNUM_UIC1C 31
/* UIC 1 */
#define VECNUM_MS (32 + 00) /* MAL SERR */
#define VECNUM_TXDE (32 + 01) /* MAL TXDE */
#define VECNUM_RXDE (32 + 02) /* MAL RXDE */
#define VECNUM_PCIE0BMVC0 (32 + 03)
#define VECNUM_PCIE0DCRERR (32 + 04)
#define VECNUM_EBC (32 + 05)
#define VECNUM_NDFC (32 + 06)
#define VECNUM_PCEI1DCRERR (32 + 07)
#define VECNUM_CT8 (32 + 08)
#define VECNUM_CT9 (32 + 09)
#define VECNUM_PCIE1AL (32 + 10)
#define VECNUM_PCIE1VPD (32 + 11)
#define VECNUM_RPCE1HRST (32 + 12)
#define VECNUM_FPCE1HRST (32 + 13)
#define VECNUM_PCIE1TCR (32 + 14)
#define VECNUM_PCIE1VC0 (32 + 15)
#define VECNUM_CT3 (32 + 16)
#define VECNUM_CT4 (32 + 17)
#define VECNUM_EIR7 (32 + 18)
#define VECNUM_EIR8 (32 + 19)
#define VECNUM_EIR9 (32 + 20)
#define VECNUM_CT5 (32 + 21)
#define VECNUM_CT6 (32 + 22)
#define VECNUM_CT7 (32 + 23)
#define VECNUM_SROM (32 + 24) /* SERIAL ROM */
#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */
#define VECNUM_EIR2 (32 + 26)
#define VECNUM_EIR5 (32 + 27)
#define VECNUM_EIR6 (32 + 28)
#define VECNUM_EMAC0WAKE (32 + 29)
#define VECNUM_EIR1 (32 + 30)
#define VECNUM_EMAC1WAKE (32 + 31)
/* UIC 2 */
#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */
#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */
#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */
#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */
#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */
#define VECNUM_DDRMCUE (64 + 05)
#define VECNUM_DDRMCCE (64 + 06)
#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */
#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */
#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */
#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */
#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */
#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */
#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */
#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */
#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */
#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */
#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */
#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */
#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */
#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */
#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */
#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */
#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */
#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */
#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */
#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */
#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */
#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */
#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */
#define VECNUM_USBWAKE (64 + 30) /* USB wakup */
#define VECNUM_USBOTG (64 + 31) /* USB OTG */
#else /* !CONFIG_405EZ */
#define VECNUM_U0 0 /* UART0 */

4
include/405_mal.h
View File

@ -92,7 +92,9 @@
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020

2
include/4xx_i2c.h
View File

@ -43,7 +43,7 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
#elif defined(CONFIG_440)
#elif defined(CONFIG_440) || defined(CONFIG_405EX)
/* all remaining 440 variants */
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
#else

4
include/asm-ppc/processor.h
View File

@ -765,6 +765,10 @@
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
#define PVR_405EZ_RA 0x41511460
#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */
#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */
#define PVR_405EX1_RA 0x12911477 /* 405EX rev A with Security */
#define PVR_405EX2_RA 0x12911475 /* 405EX rev A without Security */
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850

1
include/asm-ppc/u-boot.h
View File

@ -84,6 +84,7 @@ typedef struct bd_info {
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || \
defined(CONFIG_440)
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */

4
include/common.h
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@ -266,7 +266,7 @@ void pciinfo (int, int);
int pci_pre_init (struct pci_controller * );
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_440)
#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif
@ -274,7 +274,7 @@ void pciinfo (int, int);
void pci_master_init (struct pci_controller *);
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
#if defined(CONFIG_440SPE) || defined(CONFIG_405EX)
void pcie_setup_hoses(int busno);
#endif
#endif

675
include/ppc405.h
View File

@ -123,6 +123,40 @@
#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
#if defined(CONFIG_405EX)
#define uic0sr uicsr /* UIC status */
#define uic0srs uicsrs /* UIC status set */
#define uic0er uicer /* UIC enable */
#define uic0cr uiccr /* UIC critical */
#define uic0pr uicpr /* UIC polarity */
#define uic0tr uictr /* UIC triggering */
#define uic0msr uicmsr /* UIC masked status */
#define uic0vr uicvr /* UIC vector */
#define uic0vcr uicvcr /* UIC vector configuration*/
#define UIC_DCR_BASE1 0xd0
#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */
#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */
#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */
#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */
#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */
#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
#define UIC_DCR_BASE2 0xe0
#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */
#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */
#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */
#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */
#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */
#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/
#endif
/*-----------------------------------------------------------------------------+
| Universal interrupt controller interrupts
+-----------------------------------------------------------------------------*/
@ -166,6 +200,116 @@
#define UIC_EXT3 0x00000002 /* External interrupt 3 */
#define UIC_EXT4 0x00000001 /* External interrupt 4 */
#elif defined(CONFIG_405EX)
/* UIC 0 */
#define UIC_U0 0x80000000 /* */
#define UIC_U1 0x40000000 /* */
#define UIC_IIC0 0x20000000 /* */
#define UIC_PKA 0x10000000 /* */
#define UIC_TRNG 0x08000000 /* */
#define UIC_EBM 0x04000000 /* */
#define UIC_BGI 0x02000000 /* */
#define UIC_IIC1 0x01000000 /* */
#define UIC_SPI 0x00800000 /* */
#define UIC_EIRQ0 0x00400000 /**/
#define UIC_MTE 0x00200000 /*MAL Tx EOB */
#define UIC_MRE 0x00100000 /*MAL Rx EOB */
#define UIC_DMA0 0x00080000 /* */
#define UIC_DMA1 0x00040000 /* */
#define UIC_DMA2 0x00020000 /* */
#define UIC_DMA3 0x00010000 /* */
#define UIC_PCIE0AL 0x00008000 /* */
#define UIC_PCIE0VPD 0x00004000 /* */
#define UIC_RPCIE0HRST 0x00002000 /* */
#define UIC_FPCIE0HRST 0x00001000 /* */
#define UIC_PCIE0TCR 0x00000800 /* */
#define UIC_PCIEMSI0 0x00000400 /* */
#define UIC_PCIEMSI1 0x00000200 /* */
#define UIC_SECURITY 0x00000100 /* */
#define UIC_ENET 0x00000080 /* */
#define UIC_ENET1 0x00000040 /* */
#define UIC_PCIEMSI2 0x00000020 /* */
#define UIC_EIRQ4 0x00000010 /**/
#define UIC_UIC2NC 0x00000008 /* */
#define UIC_UIC2C 0x00000004 /* */
#define UIC_UIC1NC 0x00000002 /* */
#define UIC_UIC1C 0x00000001 /* */
#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
/* UIC 1 */
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
#define UIC_PCIE0BMVC0 0x10000000 /* */
#define UIC_PCIE0DCRERR 0x08000000 /* */
#define UIC_EBC 0x04000000 /* */
#define UIC_NDFC 0x02000000 /* */
#define UIC_PCEI1DCRERR 0x01000000 /* */
#define UIC_GPTCMPT8 0x00800000 /* */
#define UIC_GPTCMPT9 0x00400000 /* */
#define UIC_PCIE1AL 0x00200000 /* */
#define UIC_PCIE1VPD 0x00100000 /* */
#define UIC_RPCE1HRST 0x00080000 /* */
#define UIC_FPCE1HRST 0x00040000 /* */
#define UIC_PCIE1TCR 0x00020000 /* */
#define UIC_PCIE1VC0 0x00010000 /* */
#define UIC_GPTCMPT3 0x00008000 /* */
#define UIC_GPTCMPT4 0x00004000 /* */
#define UIC_EIRQ7 0x00002000 /* */
#define UIC_EIRQ8 0x00001000 /* */
#define UIC_EIRQ9 0x00000800 /* */
#define UIC_GPTCMP5 0x00000400 /* */
#define UIC_GPTCMP6 0x00000200 /* */
#define UIC_GPTCMP7 0x00000100 /* */
#define UIC_SROM 0x00000080 /* SERIAL ROM*/
#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/
#define UIC_EIRQ2 0x00000020 /* */
#define UIC_EIRQ5 0x00000010 /* */
#define UIC_EIRQ6 0x00000008 /* */
#define UIC_EMAC0WAKE 0x00000004 /* */
#define UIC_EIRQ1 0x00000002 /* */
#define UIC_EMAC1WAKE 0x00000001 /* */
#define UIC_MAL_SERR UIC_MS /* MAL SERR */
#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */
#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */
/* UIC 2 */
#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/
#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/
#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/
#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/
#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/
#define UIC_DDRMCUE 0x04000000 /* */
#define UIC_DDRMCCE 0x02000000 /* */
#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/
#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/
#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/
#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/
#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/
#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/
#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/
#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/
#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/
#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/
#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/
#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/
#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/
#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/
#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/
#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/
#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/
#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/
#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/
#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/
#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/
#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/
#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/
#define UIC_USBWAKE 0x00000002 /* USB wakup*/
#define UIC_USBOTG 0x00000001 /* USB OTG*/
#define UIC_ETH0 UIC_ENET
#define UIC_ETH1 UIC_ENET1
#else /* !defined(CONFIG_405EZ) */
#define UIC_UART0 0x80000000 /* UART 0 */
@ -256,7 +400,11 @@
/******************************************************************************
* Power Management
******************************************************************************/
#ifdef CONFIG_405EX
#define POWERMAN_DCR_BASE 0xb0
#else
#define POWERMAN_DCR_BASE 0xb8
#endif
#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
@ -561,16 +709,6 @@
#define VCO_MIN 500
#define VCO_MAX 1000
#elif defined(CONFIG_405EZ)
/******************************************************************************
* SDR Registers
******************************************************************************/
#define SDR_DCR_BASE 0x0E
#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
#define sdrnand0 0x4000
#define sdrultra0 0x4040
#define sdrultra1 0x4050
@ -1214,6 +1352,25 @@
#define GPIO1_ISR3L (GPIO1_BASE+0x40)
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#elif defined(CONFIG_405EX)
#define GPIO_BASE 0xEF600800
#define GPIO0_OR (GPIO_BASE+0x0)
#define GPIO0_TCR (GPIO_BASE+0x4)
#define GPIO0_OSRL (GPIO_BASE+0x8)
#define GPIO0_OSRH (GPIO_BASE+0xC)
#define GPIO0_TSRL (GPIO_BASE+0x10)
#define GPIO0_TSRH (GPIO_BASE+0x14)
#define GPIO0_ODR (GPIO_BASE+0x18)
#define GPIO0_IR (GPIO_BASE+0x1C)
#define GPIO0_RR1 (GPIO_BASE+0x20)
#define GPIO0_RR2 (GPIO_BASE+0x24)
#define GPIO0_ISR1L (GPIO_BASE+0x30)
#define GPIO0_ISR1H (GPIO_BASE+0x34)
#define GPIO0_ISR2L (GPIO_BASE+0x38)
#define GPIO0_ISR2H (GPIO_BASE+0x3C)
#define GPIO0_ISR3L (GPIO_BASE+0x40)
#define GPIO0_ISR3H (GPIO_BASE+0x44)
#else /* !405EZ */
#define GPIO_BASE 0xEF600700
@ -1234,33 +1391,489 @@
#endif /* CONFIG_405EZ */
/*
* Macro for accessing the indirect EBC register
*/
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
#if defined(CONFIG_405EX)
#define SDR0_SRST 0x0200
#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
#define SDRAM_BESR0 0x00
#define SDRAM_BEARL 0x02
#define SDRAM_BEARU 0x03
#define SDRAM_WMIRQ 0x06 /**/
#define SDRAM_PLBOPT 0x08 /**/
#define SDRAM_PUABA 0x09 /**/
#define SDRAM_MCSTAT 0x1F /* memory controller status */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
#define SDRAM_CODT 0x26 /* on die termination for controller */
#define SDRAM_VVPR 0x27 /* variable VRef programmming */
#define SDRAM_OPARS 0x28 /* on chip driver control setup */
#define SDRAM_OPART 0x29 /* on chip driver control trigger */
#define SDRAM_RTR 0x30 /* refresh timer */
#define SDRAM_PMIT 0x34 /* power management idle timer */
#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */
#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */
#define SDRAM_INITPLR0 0x50 /* manual initialization control */
#define SDRAM_INITPLR1 0x51 /* manual initialization control */
#define SDRAM_INITPLR2 0x52 /* manual initialization control */
#define SDRAM_INITPLR3 0x53 /* manual initialization control */
#define SDRAM_INITPLR4 0x54 /* manual initialization control */
#define SDRAM_INITPLR5 0x55 /* manual initialization control */
#define SDRAM_INITPLR6 0x56 /* manual initialization control */
#define SDRAM_INITPLR7 0x57 /* manual initialization control */
#define SDRAM_INITPLR8 0x58 /* manual initialization control */
#define SDRAM_INITPLR9 0x59 /* manual initialization control */
#define SDRAM_INITPLR10 0x5a /* manual initialization control */
#define SDRAM_INITPLR11 0x5b /* manual initialization control */
#define SDRAM_INITPLR12 0x5c /* manual initialization control */
#define SDRAM_INITPLR13 0x5d /* manual initialization control */
#define SDRAM_INITPLR14 0x5e /* manual initialization control */
#define SDRAM_INITPLR15 0x5f /* manual initialization control */
#define SDRAM_RQDC 0x70 /* read DQS delay control */
#define SDRAM_RFDC 0x74 /* read feedback delay control */
#define SDRAM_RDCC 0x78 /* read data capture control */
#define SDRAM_DLCR 0x7A /* delay line calibration */
#define SDRAM_CLKTR 0x80 /* DDR clock timing */
#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
#define SDRAM_MMODE 0x88 /* memory mode */
#define SDRAM_MEMODE 0x89 /* memory extended mode */
#define SDRAM_ECCCR 0x98 /* ECC error status */
#define SDRAM_RID 0xF8 /* revision ID */
/*-----------------------------------------------------------------------------+
| Memory Bank 0-7 configuration
+-----------------------------------------------------------------------------*/
#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */
#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */
#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */
#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */
#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */
#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */
#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */
#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */
#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */
#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */
#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */
#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */
/*-----------------------------------------------------------------------------+
| Memory Controller Status
+-----------------------------------------------------------------------------*/
#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
/*-----------------------------------------------------------------------------+
| Memory Controller Options 1
+-----------------------------------------------------------------------------*/
#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */
#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
/*-----------------------------------------------------------------------------+
| Memory Controller Options 2
+-----------------------------------------------------------------------------*/
#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
/*-----------------------------------------------------------------------------+
| SDRAM Refresh Timer Register
+-----------------------------------------------------------------------------*/
#define SDRAM_RTR_RINT_MASK 0xFFF80000
#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
/*-----------------------------------------------------------------------------+
| SDRAM Read DQS Delay Control Register
+-----------------------------------------------------------------------------*/
#define SDRAM_RQDC_RQDE_MASK 0x80000000
#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
#define SDRAM_RQDC_RQFD_MASK 0x000001FF
#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
#define SDRAM_RQDC_RQFD_MAX 0xFF
/*-----------------------------------------------------------------------------+
| SDRAM Read Data Capture Control Register
+-----------------------------------------------------------------------------*/
#define SDRAM_RDCC_RDSS_MASK 0xC0000000
#define SDRAM_RDCC_RDSS_T1 0x00000000
#define SDRAM_RDCC_RDSS_T2 0x40000000
#define SDRAM_RDCC_RDSS_T3 0x80000000
#define SDRAM_RDCC_RDSS_T4 0xC0000000
#define SDRAM_RDCC_RSAE_MASK 0x00000001
#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
/*-----------------------------------------------------------------------------+
| SDRAM Read Feedback Delay Control Register
+-----------------------------------------------------------------------------*/
#define SDRAM_RFDC_ARSE_MASK 0x80000000
#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
#define SDRAM_RFDC_RFOS_MASK 0x007F0000
#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define SDRAM_RFDC_RFFD_MASK 0x000003FF
#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define SDRAM_RFDC_RFFD_MAX 0x4FF
/*-----------------------------------------------------------------------------+
| SDRAM Delay Line Calibration Register
+-----------------------------------------------------------------------------*/
#define SDRAM_DLCR_DCLM_MASK 0x80000000
#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
#define SDRAM_DLCR_DCLM_AUTO 0x00000000
#define SDRAM_DLCR_DLCR_MASK 0x08000000
#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
#define SDRAM_DLCR_DLCR_IDLE 0x00000000
#define SDRAM_DLCR_DLCS_MASK 0x07000000
#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
#define SDRAM_DLCR_DLCS_ERROR 0x04000000
#define SDRAM_DLCR_DLCV_MASK 0x000001FF
#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
/*-----------------------------------------------------------------------------+
| SDRAM Controller On Die Termination Register
+-----------------------------------------------------------------------------*/
#define SDRAM_CODT_ODT_ON 0x80000000
#define SDRAM_CODT_ODT_OFF 0x00000000
#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
#define SDRAM_CODT_DQS_MASK 0x00000010
#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
#define SDRAM_CODT_IO_HIZ 0x00000000
#define SDRAM_CODT_IO_NMODE 0x00000001
/*-----------------------------------------------------------------------------+
| SDRAM Mode Register
+-----------------------------------------------------------------------------*/
#define SDRAM_MMODE_WR_MASK 0x00000E00
#define SDRAM_MMODE_WR_DDR1 0x00000000
#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
#define SDRAM_MMODE_DCL_MASK 0x00000070
#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
/*-----------------------------------------------------------------------------+
| SDRAM Extended Mode Register
+-----------------------------------------------------------------------------*/
#define SDRAM_MEMODE_DIC_MASK 0x00000002
#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
#define SDRAM_MEMODE_DIC_WEAK 0x00000002
#define SDRAM_MEMODE_DLL_MASK 0x00000001
#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
#define SDRAM_MEMODE_RTT_MASK 0x00000044
#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
#define SDRAM_MEMODE_RTT_75OHM 0x00000004
#define SDRAM_MEMODE_RTT_150OHM 0x00000040
#define SDRAM_MEMODE_DQS_MASK 0x00000400
#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
/*-----------------------------------------------------------------------------+
| SDRAM Clock Timing Register
+-----------------------------------------------------------------------------*/
#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
/*-----------------------------------------------------------------------------+
| SDRAM Write Timing Register
+-----------------------------------------------------------------------------*/
#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000
#define SDRAM_WRDTR_LLWP_MASK 0x10000000
#define SDRAM_WRDTR_LLWP_DIS 0x10000000
#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
#define SDRAM_WRDTR_WTR_MASK 0x0E000000
#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
/*-----------------------------------------------------------------------------+
| SDRAM SDTR1 Options
+-----------------------------------------------------------------------------*/
#define SDRAM_SDTR1_LDOF_MASK 0x80000000
#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
#define SDRAM_SDTR1_RTW_MASK 0x00F00000
#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000
#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
/*-----------------------------------------------------------------------------+
| SDRAM SDTR2 Options
+-----------------------------------------------------------------------------*/
#define SDRAM_SDTR2_RCD_MASK 0xF0000000
#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
#define SDRAM_SDTR2_WTR_MASK 0x0F000000
#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
#define SDRAM_SDTR2_WPC_MASK 0x0000F000
#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
#define SDRAM_SDTR2_RPC_MASK 0x00000F00
#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
#define SDRAM_SDTR2_RP_MASK 0x000000F0
#define SDRAM_SDTR2_RP_3_CLK 0x00000030
#define SDRAM_SDTR2_RP_4_CLK 0x00000040
#define SDRAM_SDTR2_RP_5_CLK 0x00000050
#define SDRAM_SDTR2_RP_6_CLK 0x00000060
#define SDRAM_SDTR2_RP_7_CLK 0x00000070
#define SDRAM_SDTR2_RRD_MASK 0x0000000F
#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
/*-----------------------------------------------------------------------------+
| SDRAM SDTR3 Options
+-----------------------------------------------------------------------------*/
#define SDRAM_SDTR3_RAS_MASK 0x1F000000
#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define SDRAM_SDTR3_RC_MASK 0x001F0000
#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define SDRAM_SDTR3_XCS_MASK 0x00001F00
#define SDRAM_SDTR3_XCS 0x00000D00
#define SDRAM_SDTR3_RFC_MASK 0x0000003F
#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
/*-----------------------------------------------------------------------------+
| Memory Bank 0-1 configuration
+-----------------------------------------------------------------------------*/
#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
#define sdr_uart0 0x0120 /* UART0 Config */
#define sdr_uart1 0x0121 /* UART1 Config */
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
/* Defines for CPC0_EPRCSR register */
#define CPC0_EPRCSR_E0NFE 0x80000000
#define CPC0_EPRCSR_E1NFE 0x40000000
#define CPC0_EPRCSR_E1RPP 0x00000080
#define CPC0_EPRCSR_E0RPP 0x00000040
#define CPC0_EPRCSR_E1ERP 0x00000020
#define CPC0_EPRCSR_E0ERP 0x00000010
#define CPC0_EPRCSR_E1PCI 0x00000002
#define CPC0_EPRCSR_E0PCI 0x00000001
#define cpr0_clkupd 0x020
#define cpr0_pllc 0x040
#define cpr0_plld 0x060
#define cpr0_cpud 0x080
#define cpr0_plbd 0x0a0
#define cpr0_opbd 0x0c0
#define cpr0_perd 0x0e0
#define cpr0_ahbd 0x100
#define cpr0_icfg 0x140
#define SDR_PINSTP 0x0040
#define sdr_sdcs 0x0060
#define SDR0_SDCS_SDD (0x80000000 >> 31)
/* CUST0 Customer Configuration Register0 */
#define SDR0_CUST0 0x4000
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
#endif
/******************************************************************************
* SDR Registers
******************************************************************************/
#define SDR_DCR_BASE 0x0E
#define sdrcfga (SDR_DCR_BASE+0x0)
#define sdrcfgd (SDR_DCR_BASE+0x1)
#define CPR0_DCR_BASE 0x0C
#define cprcfga (CPR0_DCR_BASE+0x0)
#define cprcfgd (CPR0_DCR_BASE+0x1)
#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
#ifndef __ASSEMBLY__
typedef struct
{
unsigned long pllFwdDiv;
unsigned long pllFwdDivB;
unsigned long pllFbkDiv;
unsigned long pllPlbDiv;
unsigned long pllPciDiv;
unsigned long pllExtBusDiv;
unsigned long pllOpbDiv;
unsigned long freqVCOMhz; /* in MHz */
unsigned long freqProcessor;
unsigned long freqPLB;
unsigned long freqPCI;
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
unsigned long pciClkSync; /* PCI clock is synchronous */
unsigned long freqVCOHz;
unsigned long pllFwdDiv;
unsigned long pllFwdDivB;
unsigned long pllFbkDiv;
unsigned long pllPlbDiv;
unsigned long pllPciDiv;
unsigned long pllExtBusDiv;
unsigned long pllOpbDiv;
unsigned long freqVCOMhz; /* in MHz */
unsigned long freqProcessor;
unsigned long freqPLB;
unsigned long freqPCI;
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
unsigned long pciClkSync; /* PCI clock is synchronous */
unsigned long freqVCOHz;
unsigned long freqOPB;
unsigned long freqEBC;
unsigned long freqDDR;
} PPC405_SYS_INFO;
#endif /* _ASMLANGUAGE */

2
include/ppc440.h
View File

@ -3345,7 +3345,7 @@ typedef struct {
unsigned long freqTmrClk;
unsigned long freqPLB;
unsigned long freqOPB;
unsigned long freqEPB;
unsigned long freqEBC;
unsigned long freqPCI;
#ifdef CONFIG_440SPE
unsigned long freqDDR;

15
include/ppc4xx_enet.h
View File

@ -146,11 +146,12 @@ typedef struct emac_4xx_hw_st {
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define SDR0_PFC1_EM_1000 (0x00200000)
#endif
/*ZMII Bridge Register addresses */
/* ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
@ -202,6 +203,8 @@ typedef struct emac_4xx_hw_st {
/* RGMII Register Addresses */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)
#elif defined(CONFIG_405EX)
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00)
#else
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)
#endif
@ -223,7 +226,8 @@ typedef struct emac_4xx_hw_st {
#define RGMII_SSR_SP_100MBPS (0x02)
#define RGMII_SSR_SP_1000MBPS (0x04)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define RGMII_SSR_V(__x) ((__x) * 8)
#else
#define RGMII_SSR_V(__x) ((__x -2) * 8)
@ -304,7 +308,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#endif
#else
#if defined(CONFIG_405EZ)
#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
#define EMAC_BASE 0xEF600900
#else
#define EMAC_BASE 0xEF600800
@ -338,7 +342,8 @@ typedef struct emac_4xx_hw_st {
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_405EX)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)

5
include/serial.h
View File

@ -22,8 +22,9 @@ extern struct serial_device serial_smc_device;
extern struct serial_device serial_scc_device;
extern struct serial_device * default_serial_console (void);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx)
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CFG_NS16550_SERIAL)