Blackfin: bf525-ucr2: new board port
Signed-off-by: Chong Huang <chuang@ucrobotics.com> Signed-off-by: Haitao Zhang <minipanda@linuxrobot.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Chong Huang
Mike Frysinger
parent
2fc32deab5
commit
dbb6d366e3
@ -1116,6 +1116,11 @@ Anton Shurpin <shurpin.aa@niistt.ru>
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BF561-ACVILON BF561
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Haitao Zhang <hzhang@ucrobotics.com>
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Chong Huang <chuang@ucrobotics.com>
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bf525-ucr2 BF525
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#########################################################################
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# End of MAINTAINERS list #
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#########################################################################
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54
board/bf525-ucr2/Makefile
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54
board/bf525-ucr2/Makefile
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y := $(BOARD).o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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16
board/bf525-ucr2/bf525-ucr2.c
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16
board/bf525-ucr2/bf525-ucr2.c
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/* U-boot - bf525-ucr2.c board specific routines
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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int checkboard(void)
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{
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printf("Board: bf525-ucr2\n");
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printf("Support: http://www.ucrobotics.com/\n");
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return 0;
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}
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@ -175,6 +175,7 @@ mimc200 avr32 at32ap - mimc
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hammerhead avr32 at32ap - miromico at32ap700x
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bct-brettl2 blackfin blackfin
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bf518f-ezbrd blackfin blackfin
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bf525-ucr2 blackfin blackfin
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bf526-ezbrd blackfin blackfin
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bf527-ad7160-eval blackfin blackfin
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bf527-ezkit blackfin blackfin
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102
include/configs/bf525-ucr2.h
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102
include/configs/bf525-ucr2.h
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/*
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* U-boot - Configuration file for bf525-ucr2 board
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* The board includes ADSP-BF525 rev. 0.2,
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* 32-bit SDRAM (SAMSUNG K4S561632H-UC75),
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* USB 2.0 High Speed OTG USB WIFI,
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* SPI flash (cFeon EN25Q128 16 MB),
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* Support PPI and ITU-R656,
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* See http://www.ucrobotics.com/?q=cn/ucr2
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*/
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#ifndef __CONFIG_BF525_UCR2_H__
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#define __CONFIG_BF525_UCR2_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf525-0.2
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 24000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 20
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 4
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 9
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#define CONFIG_MEM_SIZE 32
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/*
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* SDRAM reference page
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* http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
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*/
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#define CONFIG_EBIU_SDRRC_VAL 0x3f8
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#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
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#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
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#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
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#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
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#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (320 * 1024)
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/* We don't have a parallel flash chip */
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#define CONFIG_SYS_NO_FLASH
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/* support for serial flash */
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#define CONFIG_BFIN_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_HZ 30000000
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#define CONFIG_SPI_FLASH_EON
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_ENV_OFFSET 0x10000
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Misc Settings
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*/
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
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#define CONFIG_BOOTCOMMAND "run sfboot"
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"sfboot=sf probe 1;" \
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"sf read 0x1000000 0x20000 0x300000;" \
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"bootm 0x1000000\0"
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/* this sets up the default list of enabled commands */
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_IMLS
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#endif
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