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MIPS: mips32/cache.S: use v1 register for indirect function calls

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Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
This commit is contained in:
Gabor Juhos 2013-06-13 12:59:36 +02:00 committed by Tom Rini
parent ee8b1e2959
commit db2c86d7d7
1 changed files with 4 additions and 4 deletions
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8
arch/mips/cpu/mips32/cache.S
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@ -156,16 +156,16 @@ NESTED(mips_cache_reset, 0, ra)
*/ */
move a1, t2 move a1, t2
move a2, t8 move a2, t8
PTR_LA t7, mips_init_icache PTR_LA v1, mips_init_icache
jalr t7 jalr v1
/* /*
* then initialize D-cache. * then initialize D-cache.
*/ */
move a1, t3 move a1, t3
move a2, t8 move a2, t8
PTR_LA t7, mips_init_dcache PTR_LA v1, mips_init_dcache
jalr t7 jalr v1
jr RA jr RA
END(mips_cache_reset) END(mips_cache_reset)