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arm, am33xx: add defines for gmii_sel_register bits

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Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
This commit is contained in:
Heiko Schocher 2013-08-19 16:38:56 +02:00 committed by Tom Rini
parent 457bb50560
commit dafd4db33a
4 changed files with 22 additions and 11 deletions
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19
arch/arm/include/asm/arch-am33xx/cpu.h
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@ -486,6 +486,25 @@ struct ctrl_dev {
unsigned int resv4[4]; unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */ unsigned int miisel; /* offset 0x50 */
}; };
/* gmii_sel register defines */
#define GMII1_SEL_MII 0x0
#define GMII1_SEL_RMII 0x1
#define GMII1_SEL_RGMII 0x2
#define GMII2_SEL_MII 0x0
#define GMII2_SEL_RMII 0x4
#define GMII2_SEL_RGMII 0x8
#define RGMII1_IDMODE BIT(4)
#define RGMII2_IDMODE BIT(5)
#define RMII1_IO_CLK_EN BIT(6)
#define RMII2_IO_CLK_EN BIT(7)
#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */ #endif /* __KERNEL_STRICT_NAMES */

6
board/isee/igep0033/board.c
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@ -27,9 +27,6 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* MII mode defines */
#define RMII_MODE_ENABLE 0x4D
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
@ -158,7 +155,8 @@ int board_eth_init(bd_t *bis)
eth_setenv_enetaddr("ethaddr", mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr);
} }
writel(RMII_MODE_ENABLE, &cdev->miisel); writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
&cdev->miisel);
rv = cpsw_register(&cpsw_data); rv = cpsw_register(&cpsw_data);
if (rv < 0) if (rv < 0)

2
board/phytec/pcm051/board.c
View File

@ -31,8 +31,6 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* MII mode defines */ /* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0xA
#define RMII_RGMII2_MODE_ENABLE 0x49 #define RMII_RGMII2_MODE_ENABLE 0x49
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

6
board/ti/am335x/board.c
View File

@ -30,10 +30,6 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0x3A
/* GPIO that controls power to DDR on EVM-SK */ /* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7 #define GPIO_DDR_VTT_EN 7
@ -460,7 +456,7 @@ int board_eth_init(bd_t *bis)
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII; PHY_INTERFACE_MODE_MII;
} else { } else {
writel(RGMII_MODE_ENABLE, &cdev->miisel); writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RGMII; PHY_INTERFACE_MODE_RGMII;
} }