rockchip: Kconfig: Enable SPL support for rk3568

Enable SPL support in Kconfig and add some related option in
rk3568_common.h

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Nico Cheng 2021-10-26 10:42:19 +08:00 committed by Kever Yang
parent b774be9de5
commit daec31e5cc
3 changed files with 32 additions and 1 deletions

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@ -261,6 +261,8 @@ config ROCKCHIP_RK3399
config ROCKCHIP_RK3568 config ROCKCHIP_RK3568
bool "Support Rockchip RK3568" bool "Support Rockchip RK3568"
select ARM64 select ARM64
select SUPPORT_SPL
select SPL
select CLK select CLK
select PINCTRL select PINCTRL
select RAM select RAM

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@ -2,21 +2,43 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00a00000 CONFIG_SYS_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2 CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y CONFIG_TARGET_EVB_RK3568=y
CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y CONFIG_MISC=y
@ -30,6 +52,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000 CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SHIFT=2

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@ -16,6 +16,12 @@
#define CONFIG_IRAM_BASE 0xfdcc0000 #define CONFIG_IRAM_BASE 0xfdcc0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
#define CONFIG_SPL_STACK 0x00400000
#define CONFIG_SPL_MAX_SIZE 0x20000
#define CONFIG_SPL_BSS_START_ADDR 0x4000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_SYS_SDRAM_BASE 0