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powerpc: P1021RDB: Separate from P1_P2_RDB_PC in Kconfig

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Use TARGET_P1021RDB instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and macros.

Remove macro CONFIG_P1021RDB.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun
2016-11-17 13:43:18 -08:00
parent e9bc8a8fc1
commit da439db35a
14 changed files with 29 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
board/freescale/p1_p2_rdb_pc/Kconfig
View File

@@ -2,7 +2,8 @@ if TARGET_P1_P2_RDB_PC || \
TARGET_P1020MBG || \
TARGET_P1020RDB_PC || \
TARGET_P1020RDB_PD || \
TARGET_P1020UTM
TARGET_P1020UTM || \
TARGET_P1021RDB
config SYS_BOARD
default "p1_p2_rdb_pc"

2
board/freescale/p1_p2_rdb_pc/ddr.c
View File

@@ -15,7 +15,7 @@
#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if defined(CONFIG_P1020RDB_PROTO) || \
defined(CONFIG_P1021RDB) || \
defined(CONFIG_TARGET_P1021RDB) || \
defined(CONFIG_TARGET_P1020UTM)
/* Micron MT41J256M8_187E */
dimm_params_t ddr_raw_timing = {

12
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@@ -39,7 +39,7 @@
#define GPIO_SLIC_PIN 30
#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
#define GPIO_DDR_RST_PORT 1
#define GPIO_DDR_RST_PIN 8
#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
@@ -47,7 +47,7 @@
#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
#endif
#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
#if defined(CONFIG_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
#define PCA_IOPORT_I2C_ADDR 0x23
#define PCA_IOPORT_OUTPUT_CMD 0x2
#define PCA_IOPORT_CFG_CMD 0x6
@@ -58,7 +58,7 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GPIO */
{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
{1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
#endif
{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
@@ -150,7 +150,7 @@ void board_gpio_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
/* reset DDR3 */
setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
udelay(1000);
@@ -379,7 +379,7 @@ int board_eth_init(bd_t *bis)
}
#if defined(CONFIG_QE) && \
(defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
(defined(CONFIG_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
static void fdt_board_fixup_qe_pins(void *blob)
{
unsigned int oldbus;
@@ -448,7 +448,7 @@ int ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
sizeof("okay"), 0);
#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
#if defined(CONFIG_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
fdt_board_fixup_qe_pins(blob);
#endif
#endif