arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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@ -53,6 +53,9 @@
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#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
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#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#ifdef CONFIG_DDR_SPD
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#ifdef CONFIG_DDR_SPD
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#define CONFIG_SYS_FSL_DDR_BE
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#define CONFIG_SYS_FSL_DDR_BE
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_VERY_BIG_RAM
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13
arch/arm/include/asm/pcie_layerscape.h
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13
arch/arm/include/asm/pcie_layerscape.h
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@ -0,0 +1,13 @@
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __PCIE_LAYERSCAPE_H_
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#define __PCIE_LAYERSCAPE_H_
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void pci_init_board(void);
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void ft_pcie_setup(void *blob, bd_t *bd);
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#endif
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@ -10,6 +10,7 @@
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/pcie_layerscape.h>
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#include <mmc.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <fsl_esdhc.h>
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#include <fsl_ifc.h>
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#include <fsl_ifc.h>
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@ -258,6 +259,10 @@ int ft_board_setup(void *blob, bd_t *bd)
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{
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{
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ft_cpu_setup(blob, bd);
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCIE_LAYERSCAPE
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ft_pcie_setup(blob, bd);
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#endif
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return 0;
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return 0;
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}
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}
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@ -10,6 +10,7 @@
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/pcie_layerscape.h>
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#include <mmc.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <fsl_esdhc.h>
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#include <fsl_ifc.h>
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#include <fsl_ifc.h>
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@ -307,6 +308,10 @@ int ft_board_setup(void *blob, bd_t *bd)
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{
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{
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ft_cpu_setup(blob, bd);
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCIE_LAYERSCAPE
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ft_pcie_setup(blob, bd);
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#endif
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return 0;
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return 0;
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}
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}
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@ -17,3 +17,4 @@ obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
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obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
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obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
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obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
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obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
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obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
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obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
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obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
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51
drivers/pci/pcie_layerscape.c
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drivers/pci/pcie_layerscape.c
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Layerscape PCIe driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/pcie_layerscape.h>
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#ifdef CONFIG_OF_BOARD_SETUP
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#include <libfdt.h>
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#include <fdt_support.h>
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static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
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unsigned long ctrl_addr, enum srds_prtcl dev)
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{
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int off;
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off = fdt_node_offset_by_compat_reg(blob, pci_compat,
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(phys_addr_t)ctrl_addr);
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if (off < 0)
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return;
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if (!is_serdes_configured(dev))
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fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
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}
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void ft_pcie_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_PCIE1
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ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
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#endif
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#ifdef CONFIG_PCIE2
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ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
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#endif
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}
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#else
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void ft_pcie_setup(void *blob, bd_t *bd)
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{
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}
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#endif
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void pci_init_board(void)
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{
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}
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@ -341,6 +341,14 @@ unsigned long get_board_ddr_clk(void);
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#endif
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#endif
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#endif
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#endif
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/* PCIe */
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 /* PCIE controler 1 */
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#define CONFIG_PCIE2 /* PCIE controler 2 */
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#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_MII
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@ -236,6 +236,13 @@
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#define CONFIG_HAS_ETH2
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#define CONFIG_HAS_ETH2
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#endif
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#endif
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/* PCIe */
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 /* PCIE controler 1 */
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#define CONFIG_PCIE2 /* PCIE controler 2 */
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#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_MII
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