arm: ls102xa: Update PCIe dts node status

The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Minghuan Lian 2014-10-31 13:43:44 +08:00 committed by York Sun
parent 306fa01279
commit da419027af
8 changed files with 93 additions and 0 deletions

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@ -53,6 +53,9 @@
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#ifdef CONFIG_DDR_SPD #ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM #define CONFIG_VERY_BIG_RAM

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@ -0,0 +1,13 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PCIE_LAYERSCAPE_H_
#define __PCIE_LAYERSCAPE_H_
void pci_init_board(void);
void ft_pcie_setup(void *blob, bd_t *bd);
#endif

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@ -10,6 +10,7 @@
#include <asm/arch/immap_ls102xa.h> #include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h> #include <asm/arch/fsl_serdes.h>
#include <asm/pcie_layerscape.h>
#include <mmc.h> #include <mmc.h>
#include <fsl_esdhc.h> #include <fsl_esdhc.h>
#include <fsl_ifc.h> #include <fsl_ifc.h>
@ -258,6 +259,10 @@ int ft_board_setup(void *blob, bd_t *bd)
{ {
ft_cpu_setup(blob, bd); ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCIE_LAYERSCAPE
ft_pcie_setup(blob, bd);
#endif
return 0; return 0;
} }

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@ -10,6 +10,7 @@
#include <asm/arch/immap_ls102xa.h> #include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h> #include <asm/arch/fsl_serdes.h>
#include <asm/pcie_layerscape.h>
#include <mmc.h> #include <mmc.h>
#include <fsl_esdhc.h> #include <fsl_esdhc.h>
#include <fsl_ifc.h> #include <fsl_ifc.h>
@ -307,6 +308,10 @@ int ft_board_setup(void *blob, bd_t *bd)
{ {
ft_cpu_setup(blob, bd); ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCIE_LAYERSCAPE
ft_pcie_setup(blob, bd);
#endif
return 0; return 0;
} }

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@ -17,3 +17,4 @@ obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
obj-$(CONFIG_WINBOND_83C553) += w83c553f.o obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o

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@ -0,0 +1,51 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/pcie_layerscape.h>
#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
unsigned long ctrl_addr, enum srds_prtcl dev)
{
int off;
off = fdt_node_offset_by_compat_reg(blob, pci_compat,
(phys_addr_t)ctrl_addr);
if (off < 0)
return;
if (!is_serdes_configured(dev))
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
}
void ft_pcie_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCIE1
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
#endif
#ifdef CONFIG_PCIE2
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
#endif
}
#else
void ft_pcie_setup(void *blob, bd_t *bd)
{
}
#endif
void pci_init_board(void)
{
}

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@ -341,6 +341,14 @@ unsigned long get_board_ddr_clk(void);
#endif #endif
#endif #endif
/* PCIe */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_PCIE2 /* PCIE controler 2 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#define CONFIG_CMD_PING #define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP #define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII #define CONFIG_CMD_MII

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@ -236,6 +236,13 @@
#define CONFIG_HAS_ETH2 #define CONFIG_HAS_ETH2
#endif #endif
/* PCIe */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_PCIE2 /* PCIE controler 2 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#define CONFIG_CMD_PING #define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP #define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII #define CONFIG_CMD_MII