ARMV7: OMAP: I2C driver: Restructure i2c_read_byte function
This patch removes the "magic number" delays and instead monitors state changes in the status register bits. Signed-off-by: Steve Sakoman <steve.sakomanlinaro.org> Tested-by: Heiko Schocher <hs@denx.de>
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@ -159,58 +159,56 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
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/* no stop bit needed here */
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writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
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status = wait_for_pin ();
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if (status & I2C_STAT_XRDY) {
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/* Important: have to use byte access */
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writeb (regoffset, &i2c_base->data);
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udelay (20000);
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if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
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/* send register offset */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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if (status & I2C_STAT_XRDY) {
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/* Important: have to use byte access */
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writeb(regoffset, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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} else {
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i2c_error = 1;
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}
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if (!i2c_error) {
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writew (I2C_CON_EN, &i2c_base->con);
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while (readw(&i2c_base->stat) &
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(I2C_STAT_XRDY | I2C_STAT_ARDY)) {
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udelay (10000);
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/* Have to clear pending interrupt to clear I2C_STAT */
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writew (0xFFFF, &i2c_base->stat);
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/* set slave address */
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writew(devaddr, &i2c_base->sa);
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/* read one byte from slave */
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writew(1, &i2c_base->cnt);
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/* need stop bit here */
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writew(I2C_CON_EN | I2C_CON_MST |
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I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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/* receive data */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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/* set slave address */
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writew (devaddr, &i2c_base->sa);
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/* read one byte from slave */
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writew (1, &i2c_base->cnt);
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/* need stop bit here */
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writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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status = wait_for_pin ();
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if (status & I2C_STAT_RRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX)
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*value = readb (&i2c_base->data);
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*value = readb(&i2c_base->data);
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#else
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*value = readw (&i2c_base->data);
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*value = readw(&i2c_base->data);
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#endif
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udelay (20000);
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} else {
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i2c_error = 1;
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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if (!i2c_error) {
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writew (I2C_CON_EN, &i2c_base->con);
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while (readw (&i2c_base->stat) &
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(I2C_STAT_RRDY | I2C_STAT_ARDY)) {
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udelay (10000);
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writew (0xFFFF, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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read_exit:
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flush_fifo();
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writew (0xFFFF, &i2c_base->stat);
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writew (0, &i2c_base->cnt);
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