* Fix ICU862 environment problem

* Fix RAM size detection for RMU board

* Implement "reset" for MGT5100/MPC5200 systems
This commit is contained in:
wdenk
2003-08-28 09:41:22 +00:00
parent e0ac62d798
commit d94f92cbd7
11 changed files with 53 additions and 53 deletions

View File

@@ -25,6 +25,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#ifndef CFG_RAMBOOT
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
@@ -86,11 +87,14 @@ static void sdram_start (int hi_addr)
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
}
#endif
long int initdram (int board_type)
{
ulong test1, test2, dramsize = 0;
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* configure SDRAM start/end */
#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
@@ -133,8 +137,11 @@ long int initdram (int board_type)
#else
#ifdef CONFIG_MGT5100
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
#else
dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
#endif
#endif
#endif /* CFG_RAMBOOT */
/* return total ram size */
return dramsize;
}

View File

@@ -136,11 +136,6 @@ SECTIONS
*(.bss)
*(COMMON)
}
. = ALIGN(256 * 1024);
.ppcenv :
{
common/environment.o (.ppcenv)
}
_end = . ;
PROVIDE (end = .);
}

View File

@@ -96,7 +96,7 @@ long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size10 ;
long int size9 ;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
@@ -109,7 +109,7 @@ long int initdram (int board_type)
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
@@ -122,13 +122,20 @@ long int initdram (int board_type)
udelay (1000);
/* Check Bank 0 Memory Size
* try 10 column mode
/* Check Bank 0 Memory Size,
* 9 column mode
*/
size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
return (size10);
/*
* Final mapping:
*/
memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
udelay (1000);
return (size9);
}
/* ------------------------------------------------------------------------- */