ppc4xx: Fix problem in 44x cache POST routine
As repoted by Larry Johnson, running "diag run cache" caused a crash in U-Boot. This problem was introduced by a patch that removed the TLB entry for the cache test after the test has completed. Since this TLB was only setup once, a 2nd attempt to run this cache test failed with a crash. Now this TLB entry is created every time the routine is called. Signed-off-by: Stefan Roese <sr@denx.de>
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@ -51,8 +51,6 @@ int cache_post_test4 (int tlb, void *p, int size);
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int cache_post_test5 (int tlb, void *p, int size);
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int cache_post_test6 (int tlb, void *p, int size);
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static int tlb = -1; /* index to the victim TLB entry */
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#ifdef CONFIG_440
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static unsigned char testarea[CACHE_POST_SIZE]
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__attribute__((__aligned__(CACHE_POST_SIZE)));
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@ -60,7 +58,7 @@ __attribute__((__aligned__(CACHE_POST_SIZE)));
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int cache_post_test (int flags)
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{
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void* virt = (void*)CFG_POST_CACHE_ADDR;
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void *virt = (void *)CFG_POST_CACHE_ADDR;
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int ints;
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int res = 0;
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@ -72,26 +70,25 @@ int cache_post_test (int flags)
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*/
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#ifdef CONFIG_440
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int word0, i;
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int tlb; /* index to the victim TLB entry */
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if (tlb < 0) {
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/*
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* Allocate a new TLB entry, since we are going to modify
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* the write-through and caching inhibited storage attributes.
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*/
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program_tlb((u32)testarea, (u32)virt,
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CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
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/*
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* Allocate a new TLB entry, since we are going to modify
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* the write-through and caching inhibited storage attributes.
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*/
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program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
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TLB_WORD2_I_ENABLE);
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/* Find the TLB entry */
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for (i = 0;; i++) {
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if (i >= PPC4XX_TLB_SIZE) {
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printf ("Failed to program tlb entry\n");
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return -1;
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}
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word0 = mftlb1(i);
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if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
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tlb = i;
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break;
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}
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/* Find the TLB entry */
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for (i = 0;; i++) {
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if (i >= PPC4XX_TLB_SIZE) {
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printf ("Failed to program tlb entry\n");
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return -1;
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}
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word0 = mftlb1(i);
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if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
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tlb = i;
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break;
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}
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}
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#endif
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