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fpga: xilinx: add bitstream flags to driver desc

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Store a set of supported bitstream types in xilinx_desc structure.
It will be used to determine whether an FPGA image is able to be
loaded with a given driver.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Oleksandr Suvorov 2022-07-22 17:16:04 +03:00 committed by Michal Simek
parent f18adf1065
commit d7fcbfc19b
6 changed files with 14 additions and 7 deletions
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1
arch/arm/mach-zynq/cpu.c
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@ -22,6 +22,7 @@ xilinx_desc fpga = {
.family = xilinx_zynq, .family = xilinx_zynq,
.iface = devcfg, .iface = devcfg,
.operations = &zynq_op, .operations = &zynq_op,
.flags = FPGA_LEGACY,
}; };
#endif #endif

5
board/xilinx/versal/board.c
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@ -27,7 +27,10 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_FPGA_VERSALPL) #if defined(CONFIG_FPGA_VERSALPL)
static xilinx_desc versalpl = XILINX_VERSAL_DESC; static xilinx_desc versalpl = {
xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
FPGA_LEGACY
};
#endif #endif
int board_init(void) int board_init(void)

5
board/xilinx/zynqmp/zynqmp.c
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@ -48,7 +48,10 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; static xilinx_desc zynqmppl = {
xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL,
ZYNQMP_FPGA_FLAGS
};
#endif #endif
int __maybe_unused psu_uboot_init(void) int __maybe_unused psu_uboot_init(void)

3
include/versalpl.h
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@ -14,7 +14,4 @@
extern struct xilinx_fpga_op versal_op; extern struct xilinx_fpga_op versal_op;
#define XILINX_VERSAL_DESC \
{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
#endif /* _VERSALPL_H_ */ #endif /* _VERSALPL_H_ */

4
include/xilinx.h
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@ -37,6 +37,9 @@ typedef enum { /* typedef xilinx_family */
max_xilinx_type /* insert all new types before this */ max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */ } xilinx_family; /* end, typedef xilinx_family */
/* FPGA bitstream supported types */
#define FPGA_LEGACY BIT(0)
typedef struct { /* typedef xilinx_desc */ typedef struct { /* typedef xilinx_desc */
xilinx_family family; /* part type */ xilinx_family family; /* part type */
xilinx_iface iface; /* interface type */ xilinx_iface iface; /* interface type */
@ -45,6 +48,7 @@ typedef struct { /* typedef xilinx_desc */
int cookie; /* implementation specific cookie */ int cookie; /* implementation specific cookie */
struct xilinx_fpga_op *operations; /* operations */ struct xilinx_fpga_op *operations; /* operations */
char *name; /* device name in bitstream */ char *name; /* device name in bitstream */
int flags; /* compatible flags */
} xilinx_desc; /* end, typedef xilinx_desc */ } xilinx_desc; /* end, typedef xilinx_desc */
struct xilinx_fpga_op { struct xilinx_fpga_op {

3
include/zynqmppl.h
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@ -25,7 +25,6 @@
extern struct xilinx_fpga_op zynqmp_op; extern struct xilinx_fpga_op zynqmp_op;
#define XILINX_ZYNQMP_DESC \ #define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY)
{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
#endif /* _ZYNQMPPL_H_ */ #endif /* _ZYNQMPPL_H_ */