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Merge branch 'master' of git://git.denx.de/u-boot-mips

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This commit is contained in:
Tom Rini
2016-05-20 20:43:27 -04:00
parent d38fca40c8 40ba13c986
commit d7d0003112
79 changed files with 6448 additions and 67 deletions
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1
board/imgtec/malta/lowlevel_init.S
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@@ -24,7 +24,6 @@
.text
.set noreorder
.set mips32
.globl lowlevel_init
lowlevel_init:

12
board/qca/ap121/Kconfig Normal file
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@@ -0,0 +1,12 @@
if TARGET_AP121
config SYS_VENDOR
default "qca"
config SYS_BOARD
default "ap121"
config SYS_CONFIG_NAME
default "ap121"
endif

6
board/qca/ap121/MAINTAINERS Normal file
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@@ -0,0 +1,6 @@
AP121 BOARD
M: Wills Wang <wills.wang@live.com>
S: Maintained
F: board/qca/ap121/
F: include/configs/ap121.h
F: configs/ap121_defconfig

5
board/qca/ap121/Makefile Normal file
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@@ -0,0 +1,5 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = ap121.o

50
board/qca/ap121/ap121.c Normal file
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@@ -0,0 +1,50 @@
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/ddr.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
void __iomem *regs;
u32 val;
regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
MAP_NOCACHE);
/*
* GPIO9 as input, GPIO10 as output
*/
val = readl(regs + AR71XX_GPIO_REG_OE);
val &= ~AR933X_GPIO(9);
val |= AR933X_GPIO(10);
writel(val, regs + AR71XX_GPIO_REG_OE);
/*
* Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
*/
val = readl(regs + AR71XX_GPIO_REG_FUNC);
val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
writel(val, regs + AR71XX_GPIO_REG_FUNC);
}
#endif
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
ddr_init();
return 0;
}

12
board/qca/ap143/Kconfig Normal file
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@@ -0,0 +1,12 @@
if TARGET_AP143
config SYS_VENDOR
default "qca"
config SYS_BOARD
default "ap143"
config SYS_CONFIG_NAME
default "ap143"
endif

6
board/qca/ap143/MAINTAINERS Normal file
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@@ -0,0 +1,6 @@
AP143 BOARD
M: Wills Wang <wills.wang@live.com>
S: Maintained
F: board/qca/ap143/
F: include/configs/ap143.h
F: configs/ap143_defconfig

5
board/qca/ap143/Makefile Normal file
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@@ -0,0 +1,5 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = ap143.o

66
board/qca/ap143/ap143.c Normal file
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@@ -0,0 +1,66 @@
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/ddr.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
void __iomem *regs;
u32 val;
regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
MAP_NOCACHE);
/*
* GPIO9 as input, GPIO10 as output
*/
val = readl(regs + AR71XX_GPIO_REG_OE);
val |= QCA953X_GPIO(9);
val &= ~QCA953X_GPIO(10);
writel(val, regs + AR71XX_GPIO_REG_OE);
/*
* Enable GPIO10 as UART0_SOUT
*/
val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
val &= ~QCA953X_GPIO_MUX_MASK(16);
val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
/*
* Enable GPIO9 as UART0_SIN
*/
val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
val &= ~QCA953X_GPIO_MUX_MASK(8);
val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
/*
* Enable GPIO10 output
*/
val = readl(regs + AR71XX_GPIO_REG_OUT);
val |= QCA953X_GPIO(10);
writel(val, regs + AR71XX_GPIO_REG_OUT);
}
#endif
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
ddr_init();
return 0;
}

15
board/tplink/wdr4300/Kconfig Normal file
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@@ -0,0 +1,15 @@
if BOARD_TPLINK_WDR4300
config SYS_VENDOR
default "tplink"
config SYS_SOC
default "ath79"
config SYS_BOARD
default "wdr4300"
config SYS_CONFIG_NAME
default "tplink_wdr4300"
endif

6
board/tplink/wdr4300/MAINTAINERS Normal file
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@@ -0,0 +1,6 @@
TPLINK_WDR4300 BOARD
M: Marek Vasut <marex@denx.de>
S: Maintained
F: board/tplink/wdr4300/
F: include/configs/tplink_wdr4300.h
F: configs/tplink_wdr4300_defconfig

5
board/tplink/wdr4300/Makefile Normal file
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@@ -0,0 +1,5 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = wdr4300.o

74
board/tplink/wdr4300/wdr4300.c Normal file
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@@ -0,0 +1,74 @@
/*
* Copyright (C) 2016 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ath79.h>
#include <mach/ar71xx_regs.h>
#include <mach/ddr.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB
static void wdr4300_usb_start(void)
{
void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
AR71XX_GPIO_SIZE, MAP_NOCACHE);
if (!gpio_regs)
return;
/* Power up the USB HUB. */
clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
mdelay(1);
ath79_usb_reset();
}
#else
static inline void wdr4300_usb_start(void) {}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
void __iomem *regs;
regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
MAP_NOCACHE);
/* Assure JTAG is not disconnected. */
writel(0x40, regs + AR934X_GPIO_REG_FUNC);
/* Configure default GPIO input/output regs. */
writel(0x3031b, regs + AR71XX_GPIO_REG_OE);
writel(0x0f804, regs + AR71XX_GPIO_REG_OUT);
/* Configure pin multiplexing. */
writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0);
writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1);
writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2);
writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
ar934x_pll_init(560, 480, 240);
ar934x_ddr_init(560, 480, 240);
#endif
wdr4300_usb_start();
ath79_eth_reset();
return 0;
}
#endif