spi: spi-mxc: add defines for clk inactive state for ECSPI
Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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@ -230,9 +230,10 @@
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_POL 4
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#define MXC_CSPICON_PHA 0
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#define MXC_CSPICON_SSPOL 12
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#define MXC_CSPICON_PHA 0 /* SCLK phase control */
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#define MXC_SPI_BASE_ADDRESSES \
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CSPI1_BASE_ADDR, \
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CSPI2_BASE_ADDR, \
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@ -405,9 +405,10 @@ struct cspi_regs {
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_POL 4
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#define MXC_CSPICON_PHA 0
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#define MXC_CSPICON_SSPOL 12
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#define MXC_CSPICON_PHA 0 /* SCLK phase control */
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#ifdef CONFIG_MX6SL
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#define MXC_SPI_BASE_ADDRESSES \
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ECSPI1_BASE_ADDR, \
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