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Merge http://git.denx.de/u-boot-samsung

Browse Source 
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/peach-pi_defconfig
	configs/peach-pit_defconfig
This commit is contained in:
Tom Rini
2016-06-06 13:24:23 -04:00
parent 65eac4cc54 086e13c5f6
commit d77fa2ff76
101 changed files with 3140 additions and 1485 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/video/Makefile
View File

@@ -25,11 +25,6 @@ obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
exynos_mipi_dsi_lowlevel.o
obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
obj-$(CONFIG_L5F31188) += l5f31188.o
@@ -68,6 +63,7 @@ obj-$(CONFIG_LG4573) += lg4573.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
obj-${CONFIG_EXYNOS_FB} += exynos/
obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
obj-y += bridge/

12
drivers/video/exynos/Makefile Normal file
View File

@@ -0,0 +1,12 @@
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o
obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
exynos_mipi_dsi_lowlevel.o
obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o

599
drivers/video/exynos_dp.c → drivers/video/exynos/exynos_dp.c
View File

File diff suppressed because it is too large Load Diff

266
drivers/video/exynos_dp_lowlevel.c → drivers/video/exynos/exynos_dp_lowlevel.c
View File

@@ -14,30 +14,13 @@
#include <asm/arch/dp.h>
#include <fdtdec.h>
#include <libfdt.h>
#include "exynos_dp_lowlevel.h"
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
struct exynos_dp *dp_regs;
void exynos_dp_set_base_addr(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
0, COMPAT_SAMSUNG_EXYNOS5_DP);
if (node <= 0)
debug("exynos_dp: Can't get device node for dp\n");
dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob,
node, "reg");
if (dp_regs == NULL)
debug("Can't get the DP base address\n");
#else
dp_regs = (struct exynos_dp *)samsung_get_base_dp();
#endif
}
static void exynos_dp_enable_video_input(unsigned int enable)
static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
unsigned int enable)
{
unsigned int reg;
@@ -53,7 +36,7 @@ static void exynos_dp_enable_video_input(unsigned int enable)
return;
}
void exynos_dp_enable_video_bist(unsigned int enable)
void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable)
{
/* enable video bist */
unsigned int reg;
@@ -70,7 +53,7 @@ void exynos_dp_enable_video_bist(unsigned int enable)
return;
}
void exynos_dp_enable_video_mute(unsigned int enable)
void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable)
{
unsigned int reg;
@@ -85,7 +68,7 @@ void exynos_dp_enable_video_mute(unsigned int enable)
}
static void exynos_dp_init_analog_param(void)
static void exynos_dp_init_analog_param(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -134,7 +117,7 @@ static void exynos_dp_init_analog_param(void)
writel(reg, &dp_regs->pll_ctl);
}
static void exynos_dp_init_interrupt(void)
static void exynos_dp_init_interrupt(struct exynos_dp *dp_regs)
{
/* Set interrupt registers to initial states */
@@ -161,16 +144,16 @@ static void exynos_dp_init_interrupt(void)
writel(0x00, &dp_regs->int_sta_mask);
}
void exynos_dp_reset(void)
void exynos_dp_reset(struct exynos_dp *dp_regs)
{
unsigned int reg_func_1;
/* dp tx sw reset */
writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
exynos_dp_enable_video_input(DP_DISABLE);
exynos_dp_enable_video_bist(DP_DISABLE);
exynos_dp_enable_video_mute(DP_DISABLE);
exynos_dp_enable_video_input(dp_regs, DP_DISABLE);
exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
/* software reset */
reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
@@ -182,13 +165,13 @@ void exynos_dp_reset(void)
mdelay(1);
exynos_dp_init_analog_param();
exynos_dp_init_interrupt();
exynos_dp_init_analog_param(dp_regs);
exynos_dp_init_interrupt(dp_regs);
return;
}
void exynos_dp_enable_sw_func(unsigned int enable)
void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable)
{
unsigned int reg;
@@ -203,7 +186,8 @@ void exynos_dp_enable_sw_func(unsigned int enable)
return;
}
unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
unsigned int block, u32 enable)
{
unsigned int reg;
@@ -256,7 +240,7 @@ unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
return 0;
}
unsigned int exynos_dp_get_pll_lock_status(void)
unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -268,7 +252,8 @@ unsigned int exynos_dp_get_pll_lock_status(void)
return PLL_UNLOCKED;
}
static void exynos_dp_set_pll_power(unsigned int enable)
static void exynos_dp_set_pll_power(struct exynos_dp *dp_regs,
unsigned int enable)
{
unsigned int reg;
@@ -281,14 +266,14 @@ static void exynos_dp_set_pll_power(unsigned int enable)
writel(reg, &dp_regs->pll_ctl);
}
int exynos_dp_init_analog_func(void)
int exynos_dp_init_analog_func(struct exynos_dp *dp_regs)
{
int ret = EXYNOS_DP_SUCCESS;
unsigned int retry_cnt = 10;
unsigned int reg;
/* Power On All Analog block */
exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, DP_DISABLE);
reg = PLL_LOCK_CHG;
writel(reg, &dp_regs->common_int_sta1);
@@ -309,9 +294,9 @@ int exynos_dp_init_analog_func(void)
reg &= ~(DP_PLL_RESET);
writel(reg, &dp_regs->pll_ctl);
exynos_dp_set_pll_power(DP_ENABLE);
exynos_dp_set_pll_power(dp_regs, DP_ENABLE);
while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
while (exynos_dp_get_pll_lock_status(dp_regs) == PLL_UNLOCKED) {
mdelay(1);
retry_cnt--;
if (retry_cnt == 0) {
@@ -332,7 +317,7 @@ int exynos_dp_init_analog_func(void)
return ret;
}
void exynos_dp_init_hpd(void)
void exynos_dp_init_hpd(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -350,7 +335,7 @@ void exynos_dp_init_hpd(void)
return;
}
static inline void exynos_dp_reset_aux(void)
static inline void exynos_dp_reset_aux(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -362,7 +347,7 @@ static inline void exynos_dp_reset_aux(void)
return;
}
void exynos_dp_init_aux(void)
void exynos_dp_init_aux(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -370,7 +355,7 @@ void exynos_dp_init_aux(void)
reg = RPLY_RECEIV | AUX_ERR;
writel(reg, &dp_regs->int_sta);
exynos_dp_reset_aux();
exynos_dp_reset_aux(dp_regs);
/* Disable AUX transaction H/W retry */
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
@@ -389,7 +374,7 @@ void exynos_dp_init_aux(void)
return;
}
void exynos_dp_config_interrupt(void)
void exynos_dp_config_interrupt(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -412,7 +397,7 @@ void exynos_dp_config_interrupt(void)
return;
}
unsigned int exynos_dp_get_plug_in_status(void)
unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -423,13 +408,13 @@ unsigned int exynos_dp_get_plug_in_status(void)
return -1;
}
unsigned int exynos_dp_detect_hpd(void)
unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs)
{
int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
mdelay(2);
while (exynos_dp_get_plug_in_status() != 0) {
while (exynos_dp_get_plug_in_status(dp_regs) != 0) {
if (timeout_loop == 0)
return -EINVAL;
mdelay(10);
@@ -439,7 +424,7 @@ unsigned int exynos_dp_detect_hpd(void)
return EXYNOS_DP_SUCCESS;
}
unsigned int exynos_dp_start_aux_transaction(void)
unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs)
{
unsigned int reg;
unsigned int ret = 0;
@@ -488,8 +473,9 @@ unsigned int exynos_dp_start_aux_transaction(void)
return EXYNOS_DP_SUCCESS;
}
unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
unsigned char data)
unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
unsigned int reg_addr,
unsigned char data)
{
unsigned int reg, ret;
@@ -518,7 +504,7 @@ unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
writel(reg, &dp_regs->aux_ch_ctl1);
/* Start AUX transaction */
ret = exynos_dp_start_aux_transaction();
ret = exynos_dp_start_aux_transaction(dp_regs);
if (ret != EXYNOS_DP_SUCCESS) {
printf("DP Aux transaction failed\n");
return ret;
@@ -527,8 +513,9 @@ unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
return ret;
}
unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
unsigned char *data)
unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
unsigned int reg_addr,
unsigned char *data)
{
unsigned int reg;
int retval;
@@ -554,7 +541,7 @@ unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
writel(reg, &dp_regs->aux_ch_ctl1);
/* Start AUX transaction */
retval = exynos_dp_start_aux_transaction();
retval = exynos_dp_start_aux_transaction(dp_regs);
if (!retval)
debug("DP Aux Transaction fail!\n");
@@ -565,9 +552,10 @@ unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
return retval;
}
unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
unsigned int count,
unsigned char data[])
unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
unsigned int reg_addr,
unsigned int count,
unsigned char data[])
{
unsigned int reg;
unsigned int start_offset;
@@ -614,7 +602,7 @@ unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
writel(reg, &dp_regs->aux_ch_ctl1);
/* Start AUX transaction */
ret = exynos_dp_start_aux_transaction();
ret = exynos_dp_start_aux_transaction(dp_regs);
if (ret != EXYNOS_DP_SUCCESS) {
if (retry_cnt == 0) {
printf("DP Aux Transaction failed\n");
@@ -630,9 +618,10 @@ unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
return ret;
}
unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
unsigned int count,
unsigned char data[])
unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
unsigned int reg_addr,
unsigned int count,
unsigned char data[])
{
unsigned int reg;
unsigned int start_offset;
@@ -672,7 +661,7 @@ unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
writel(reg, &dp_regs->aux_ch_ctl1);
/* Start AUX transaction */
ret = exynos_dp_start_aux_transaction();
ret = exynos_dp_start_aux_transaction(dp_regs);
if (ret != EXYNOS_DP_SUCCESS) {
if (retry_cnt == 0) {
printf("DP Aux Transaction failed\n");
@@ -696,8 +685,8 @@ unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
return ret;
}
int exynos_dp_select_i2c_device(unsigned int device_addr,
unsigned int reg_addr)
int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
unsigned int device_addr, unsigned int reg_addr)
{
unsigned int reg;
int retval;
@@ -721,16 +710,16 @@ int exynos_dp_select_i2c_device(unsigned int device_addr,
writel(reg, &dp_regs->aux_ch_ctl1);
/* Start AUX transaction */
retval = exynos_dp_start_aux_transaction();
retval = exynos_dp_start_aux_transaction(dp_regs);
if (retval != 0)
printf("%s: DP Aux Transaction fail!\n", __func__);
return retval;
}
int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
unsigned int reg_addr,
unsigned int *data)
int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
unsigned int device_addr,
unsigned int reg_addr, unsigned int *data)
{
unsigned int reg;
int i;
@@ -742,7 +731,8 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
writel(reg, &dp_regs->buffer_data_ctl);
/* Select EDID device */
retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
retval = exynos_dp_select_i2c_device(dp_regs, device_addr,
reg_addr);
if (retval != 0) {
printf("DP Select EDID device fail. retry !\n");
continue;
@@ -758,7 +748,7 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
writel(reg, &dp_regs->aux_ch_ctl1);
/* Start AUX transaction */
retval = exynos_dp_start_aux_transaction();
retval = exynos_dp_start_aux_transaction(dp_regs);
if (retval != EXYNOS_DP_SUCCESS)
printf("%s: DP Aux Transaction fail!\n", __func__);
}
@@ -770,8 +760,10 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
return retval;
}
int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
unsigned int reg_addr, unsigned int count, unsigned char edid[])
int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
unsigned int device_addr,
unsigned int reg_addr, unsigned int count,
unsigned char edid[])
{
unsigned int reg;
unsigned int i, j;
@@ -795,9 +787,8 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
* request without sending addres
*/
if (!defer)
retval =
exynos_dp_select_i2c_device(device_addr,
reg_addr + i);
retval = exynos_dp_select_i2c_device(
dp_regs, device_addr, reg_addr + i);
else
defer = 0;
@@ -813,7 +804,8 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
writel(reg, &dp_regs->aux_ch_ctl1);
/* Start AUX transaction */
retval = exynos_dp_start_aux_transaction();
retval = exynos_dp_start_aux_transaction(
dp_regs);
if (retval == 0)
break;
else
@@ -838,7 +830,7 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
return retval;
}
void exynos_dp_reset_macro(void)
void exynos_dp_reset_macro(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -853,7 +845,8 @@ void exynos_dp_reset_macro(void)
writel(reg, &dp_regs->phy_test);
}
void exynos_dp_set_link_bandwidth(unsigned char bwtype)
void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
unsigned char bwtype)
{
unsigned int reg;
@@ -864,7 +857,7 @@ void exynos_dp_set_link_bandwidth(unsigned char bwtype)
writel(reg, &dp_regs->link_bw_set);
}
unsigned char exynos_dp_get_link_bandwidth(void)
unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs)
{
unsigned char ret;
unsigned int reg;
@@ -875,7 +868,7 @@ unsigned char exynos_dp_get_link_bandwidth(void)
return ret;
}
void exynos_dp_set_lane_count(unsigned char count)
void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count)
{
unsigned int reg;
@@ -886,7 +879,7 @@ void exynos_dp_set_lane_count(unsigned char count)
writel(reg, &dp_regs->lane_count_set);
}
unsigned int exynos_dp_get_lane_count(void)
unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -895,7 +888,8 @@ unsigned int exynos_dp_get_lane_count(void)
return reg;
}
unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
unsigned char lanecnt)
{
unsigned int reg_list[DP_LANE_CNT_4] = {
(unsigned int)&dp_regs->ln0_link_training_ctl,
@@ -907,8 +901,9 @@ unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
return readl(reg_list[lanecnt]);
}
void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
unsigned char lanecnt)
void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
unsigned char request_val,
unsigned char lanecnt)
{
unsigned int reg_list[DP_LANE_CNT_4] = {
(unsigned int)&dp_regs->ln0_link_training_ctl,
@@ -920,7 +915,8 @@ void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
writel(request_val, reg_list[lanecnt]);
}
void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
unsigned int level, unsigned char lanecnt)
{
unsigned char i;
unsigned int reg;
@@ -943,7 +939,8 @@ void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
}
}
void exynos_dp_set_training_pattern(unsigned int pattern)
void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
unsigned int pattern)
{
unsigned int reg = 0;
@@ -971,7 +968,8 @@ void exynos_dp_set_training_pattern(unsigned int pattern)
writel(reg, &dp_regs->training_ptn_set);
}
void exynos_dp_enable_enhanced_mode(unsigned char enable)
void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
unsigned char enable)
{
unsigned int reg;
@@ -984,7 +982,7 @@ void exynos_dp_enable_enhanced_mode(unsigned char enable)
writel(reg, &dp_regs->sys_ctl4);
}
void exynos_dp_enable_scrambling(unsigned int enable)
void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable)
{
unsigned int reg;
@@ -997,7 +995,7 @@ void exynos_dp_enable_scrambling(unsigned int enable)
writel(reg, &dp_regs->training_ptn_set);
}
int exynos_dp_init_video(void)
int exynos_dp_init_video(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -1012,7 +1010,8 @@ int exynos_dp_init_video(void)
return 0;
}
void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
struct edp_video_info *video_info)
{
unsigned int reg;
@@ -1045,7 +1044,8 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
writel(reg, &dp_regs->soc_general_ctl);
}
void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
struct edp_video_info *video_info)
{
unsigned int reg;
@@ -1065,49 +1065,47 @@ void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
writel(reg, &dp_regs->video_ctl3);
}
int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
struct exynos_dp_priv *priv)
{
unsigned int reg;
unsigned int bist_type = 0;
struct edp_video_info video_info = edp_info->video_info;
struct edp_video_info video_info = priv->video_info;
/* For master mode, you don't need to set the video format */
if (video_info.master_mode == 0) {
writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
&dp_regs->total_ln_cfg_l);
writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
&dp_regs->total_ln_cfg_h);
writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
&dp_regs->active_ln_cfg_l);
writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
&dp_regs->active_ln_cfg_h);
writel(edp_info->disp_info.v_sync_width,
&dp_regs->vsw_cfg);
writel(edp_info->disp_info.v_back_porch,
&dp_regs->vbp_cfg);
writel(edp_info->disp_info.v_front_porch,
&dp_regs->vfp_cfg);
writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total),
&dp_regs->total_ln_cfg_l);
writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total),
&dp_regs->total_ln_cfg_h);
writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res),
&dp_regs->active_ln_cfg_l);
writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res),
&dp_regs->active_ln_cfg_h);
writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg);
writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg);
writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg);
writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
&dp_regs->total_pix_cfg_l);
writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
&dp_regs->total_pix_cfg_h);
writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
&dp_regs->active_pix_cfg_l);
writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
&dp_regs->active_pix_cfg_h);
writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
&dp_regs->hfp_cfg_l);
writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
&dp_regs->hfp_cfg_h);
writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
&dp_regs->hsw_cfg_l);
writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
&dp_regs->hsw_cfg_h);
writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
&dp_regs->hbp_cfg_l);
writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
&dp_regs->hbp_cfg_h);
writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total),
&dp_regs->total_pix_cfg_l);
writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total),
&dp_regs->total_pix_cfg_h);
writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res),
&dp_regs->active_pix_cfg_l);
writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res),
&dp_regs->active_pix_cfg_h);
writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch),
&dp_regs->hfp_cfg_l);
writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch),
&dp_regs->hfp_cfg_h);
writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width),
&dp_regs->hsw_cfg_l);
writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width),
&dp_regs->hsw_cfg_h);
writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch),
&dp_regs->hbp_cfg_l);
writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch),
&dp_regs->hbp_cfg_h);
/*
* Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
@@ -1155,7 +1153,7 @@ int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
return 0;
}
unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
unsigned int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -1173,8 +1171,8 @@ unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
return EXYNOS_DP_SUCCESS;
}
void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
unsigned int n_value)
void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
unsigned int m_value, unsigned int n_value)
{
unsigned int reg;
@@ -1202,7 +1200,8 @@ void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
}
}
void exynos_dp_set_video_timing_mode(unsigned int type)
void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
unsigned int type)
{
unsigned int reg;
@@ -1215,7 +1214,8 @@ void exynos_dp_set_video_timing_mode(unsigned int type)
writel(reg, &dp_regs->video_ctl10);
}
void exynos_dp_enable_video_master(unsigned int enable)
void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
unsigned int enable)
{
unsigned int reg;
@@ -1231,7 +1231,7 @@ void exynos_dp_enable_video_master(unsigned int enable)
writel(reg, &dp_regs->soc_general_ctl);
}
void exynos_dp_start_video(void)
void exynos_dp_start_video(struct exynos_dp *dp_regs)
{
unsigned int reg;
@@ -1241,7 +1241,7 @@ void exynos_dp_start_video(void)
writel(reg, &dp_regs->video_ctl1);
}
unsigned int exynos_dp_is_video_stream_on(void)
unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs)
{
unsigned int reg;

89
drivers/video/exynos/exynos_dp_lowlevel.h Normal file
View File

@@ -0,0 +1,89 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EXYNOS_EDP_LOWLEVEL_H
#define _EXYNOS_EDP_LOWLEVEL_H
void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs,
unsigned int enable);
void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs,
unsigned int enable);
void exynos_dp_reset(struct exynos_dp *dp_regs);
void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable);
unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
unsigned int block, u32 enable);
unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs);
int exynos_dp_init_analog_func(struct exynos_dp *dp_regs);
void exynos_dp_init_hpd(struct exynos_dp *dp_regs);
void exynos_dp_init_aux(struct exynos_dp *dp_regs);
void exynos_dp_config_interrupt(struct exynos_dp *dp_regs);
unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs);
unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs);
unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs);
unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
unsigned int reg_addr,
unsigned char data);
unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
unsigned int reg_addr,
unsigned char *data);
unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
unsigned int device_addr,
unsigned int reg_addr);
int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
unsigned int device_addr,
unsigned int reg_addr, unsigned int *data);
int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
unsigned int device_addr,
unsigned int reg_addr, unsigned int count,
unsigned char edid[]);
void exynos_dp_reset_macro(struct exynos_dp *dp_regs);
void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
unsigned char bwtype);
unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs);
void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count);
unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs);
unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
unsigned char lanecnt);
void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
unsigned int level, unsigned char lanecnt);
void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
unsigned char request_val,
unsigned char lanecnt);
void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
unsigned int pattern);
void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
unsigned char enable);
void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs,
unsigned int enable);
int exynos_dp_init_video(struct exynos_dp *dp_regs);
void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
struct edp_video_info *video_info);
void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
struct edp_video_info *video_info);
int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
struct exynos_dp_priv *priv);
unsigned int exynos_dp_is_slave_video_stream_clock_on(
struct exynos_dp *dp_regs);
void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
unsigned int m_value, unsigned int n_value);
void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
unsigned int type);
void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
unsigned int enable);
void exynos_dp_start_video(struct exynos_dp *dp_regs);
unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs);
#endif /* _EXYNOS_DP_LOWLEVEL_H */

720
drivers/video/exynos/exynos_fb.c Normal file
View File

@@ -0,0 +1,720 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: InKi Dae <inki.dae@samsung.com>
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <display.h>
#include <div64.h>
#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <panel.h>
#include <video.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/fb.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/system.h>
#include <asm/gpio.h>
#include <asm-generic/errno.h>
DECLARE_GLOBAL_DATA_PTR;
enum {
FIMD_RGB_INTERFACE = 1,
FIMD_CPU_INTERFACE = 2,
};
enum exynos_fb_rgb_mode_t {
MODE_RGB_P = 0,
MODE_BGR_P = 1,
MODE_RGB_S = 2,
MODE_BGR_S = 3,
};
struct exynos_fb_priv {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
ushort vl_width; /* Width of display area in millimeters */
ushort vl_height; /* Height of display area in millimeters */
/* LCD configuration register */
u_char vl_freq; /* Frequency */
u_char vl_clkp; /* Clock polarity */
u_char vl_oep; /* Output Enable polarity */
u_char vl_hsp; /* Horizontal Sync polarity */
u_char vl_vsp; /* Vertical Sync polarity */
u_char vl_dp; /* Data polarity */
u_char vl_bpix; /* Bits per pixel */
/* Horizontal control register. Timing from data sheet */
u_char vl_hspw; /* Horz sync pulse width */
u_char vl_hfpd; /* Wait before of line */
u_char vl_hbpd; /* Wait end of line */
/* Vertical control register. */
u_char vl_vspw; /* Vertical sync pulse width */
u_char vl_vfpd; /* Wait before of frame */
u_char vl_vbpd; /* Wait end of frame */
u_char vl_cmd_allow_len; /* Wait end of frame */
unsigned int win_id;
unsigned int init_delay;
unsigned int power_on_delay;
unsigned int reset_delay;
unsigned int interface_mode;
unsigned int mipi_enabled;
unsigned int dp_enabled;
unsigned int cs_setup;
unsigned int wr_setup;
unsigned int wr_act;
unsigned int wr_hold;
unsigned int logo_on;
unsigned int logo_width;
unsigned int logo_height;
int logo_x_offset;
int logo_y_offset;
unsigned long logo_addr;
unsigned int rgb_mode;
unsigned int resolution;
/* parent clock name(MPLL, EPLL or VPLL) */
unsigned int pclk_name;
/* ratio value for source clock from parent clock. */
unsigned int sclk_div;
unsigned int dual_lcd_enabled;
struct exynos_fb *reg;
struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
};
static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
if (enabled) {
cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
EXYNOS_DUALRGB_VDEN_EN_ENABLE;
/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) |
EXYNOS_DUALRGB_MAIN_CNT(0);
}
writel(cfg, &reg->dualrgb);
}
static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv,
unsigned int enabled)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
if (enabled)
cfg = EXYNOS_DP_CLK_ENABLE;
writel(cfg, &reg->dp_mie_clkcon);
}
static void exynos_fimd_set_par(struct exynos_fb_priv *priv,
unsigned int win_id)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
/* set window control */
cfg = readl((unsigned int)&reg->wincon0 +
EXYNOS_WINCON(win_id));
cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
/* DATAPATH is DMA */
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
/* dma burst is 16 */
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
switch (priv->vl_bpix) {
case 4:
cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
break;
default:
cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
break;
}
writel(cfg, (unsigned int)&reg->wincon0 +
EXYNOS_WINCON(win_id));
/* set window position to x=0, y=0*/
cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
writel(cfg, (unsigned int)&reg->vidosd0a +
EXYNOS_VIDOSD(win_id));
cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) |
EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) |
EXYNOS_VIDOSD_RIGHT_X_E(1) |
EXYNOS_VIDOSD_BOTTOM_Y_E(0);
writel(cfg, (unsigned int)&reg->vidosd0b +
EXYNOS_VIDOSD(win_id));
/* set window size for window0*/
cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row);
writel(cfg, (unsigned int)&reg->vidosd0c +
EXYNOS_VIDOSD(win_id));
}
static void exynos_fimd_set_buffer_address(struct exynos_fb_priv *priv,
unsigned int win_id,
ulong lcd_base_addr)
{
struct exynos_fb *reg = priv->reg;
unsigned long start_addr, end_addr;
start_addr = lcd_base_addr;
end_addr = start_addr + ((priv->vl_col * (VNBITS(priv->vl_bpix) / 8)) *
priv->vl_row);
writel(start_addr, (unsigned int)&reg->vidw00add0b0 +
EXYNOS_BUFFER_OFFSET(win_id));
writel(end_addr, (unsigned int)&reg->vidw00add1b0 +
EXYNOS_BUFFER_OFFSET(win_id));
}
static void exynos_fimd_set_clock(struct exynos_fb_priv *priv)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0, div = 0, remainder, remainder_div;
unsigned long pixel_clock;
unsigned long long src_clock;
if (priv->dual_lcd_enabled) {
pixel_clock = priv->vl_freq *
(priv->vl_hspw + priv->vl_hfpd +
priv->vl_hbpd + priv->vl_col / 2) *
(priv->vl_vspw + priv->vl_vfpd +
priv->vl_vbpd + priv->vl_row);
} else if (priv->interface_mode == FIMD_CPU_INTERFACE) {
pixel_clock = priv->vl_freq *
priv->vl_width * priv->vl_height *
(priv->cs_setup + priv->wr_setup +
priv->wr_act + priv->wr_hold + 1);
} else {
pixel_clock = priv->vl_freq *
(priv->vl_hspw + priv->vl_hfpd +
priv->vl_hbpd + priv->vl_col) *
(priv->vl_vspw + priv->vl_vfpd +
priv->vl_vbpd + priv->vl_row);
}
cfg = readl(&reg->vidcon0);
cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
EXYNOS_VIDCON0_CLKDIR_MASK);
cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
src_clock = (unsigned long long) get_lcd_clk();
/* get quotient and remainder. */
remainder = do_div(src_clock, pixel_clock);
div = src_clock;
remainder *= 10;
remainder_div = remainder / pixel_clock;
/* round about one places of decimals. */
if (remainder_div >= 5)
div++;
/* in case of dual lcd mode. */
if (priv->dual_lcd_enabled)
div--;
cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
writel(cfg, &reg->vidcon0);
}
void exynos_set_trigger(struct exynos_fb_priv *priv)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
cfg = readl(&reg->trigcon);
cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
writel(cfg, &reg->trigcon);
}
int exynos_is_i80_frame_done(struct exynos_fb_priv *priv)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
int status;
cfg = readl(&reg->trigcon);
/* frame done func is valid only when TRIMODE[0] is set to 1. */
status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
EXYNOS_I80STATUS_TRIG_DONE;
return status;
}
static void exynos_fimd_lcd_on(struct exynos_fb_priv *priv)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
/* display on */
cfg = readl(&reg->vidcon0);
cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
writel(cfg, &reg->vidcon0);
}
static void exynos_fimd_window_on(struct exynos_fb_priv *priv,
unsigned int win_id)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
/* enable window */
cfg = readl((unsigned int)&reg->wincon0 +
EXYNOS_WINCON(win_id));
cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
writel(cfg, (unsigned int)&reg->wincon0 +
EXYNOS_WINCON(win_id));
cfg = readl(&reg->winshmap);
cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
writel(cfg, &reg->winshmap);
}
void exynos_fimd_lcd_off(struct exynos_fb_priv *priv)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
cfg = readl(&reg->vidcon0);
cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
writel(cfg, &reg->vidcon0);
}
void exynos_fimd_window_off(struct exynos_fb_priv *priv, unsigned int win_id)
{
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0;
cfg = readl((unsigned int)&reg->wincon0 +
EXYNOS_WINCON(win_id));
cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
writel(cfg, (unsigned int)&reg->wincon0 +
EXYNOS_WINCON(win_id));
cfg = readl(&reg->winshmap);
cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
writel(cfg, &reg->winshmap);
}
/*
* The reset value for FIMD SYSMMU register MMU_CTRL is 3
* on Exynos5420 and newer versions.
* This means FIMD SYSMMU is on by default on Exynos5420
* and newer versions.
* Since in u-boot we don't use SYSMMU, we should disable
* those FIMD SYSMMU.
* Note that there are 2 SYSMMU for FIMD: m0 and m1.
* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
* We disable both of them here.
*/
void exynos_fimd_disable_sysmmu(void)
{
u32 *sysmmufimd;
unsigned int node;
int node_list[2];
int count;
int i;
count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
for (i = 0; i < count; i++) {
node = node_list[i];
if (node <= 0) {
debug("Can't get device node for fimd sysmmu\n");
return;
}
sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
if (!sysmmufimd) {
debug("Can't get base address for sysmmu fimdm0");
return;
}
writel(0x0, sysmmufimd);
}
}
void exynos_fimd_lcd_init(struct udevice *dev)
{
struct exynos_fb_priv *priv = dev_get_priv(dev);
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct exynos_fb *reg = priv->reg;
unsigned int cfg = 0, rgb_mode;
unsigned int offset;
unsigned int node;
node = dev->of_offset;
if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
exynos_fimd_disable_sysmmu();
offset = exynos_fimd_get_base_offset();
rgb_mode = priv->rgb_mode;
if (priv->interface_mode == FIMD_RGB_INTERFACE) {
cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
writel(cfg, &reg->vidcon0);
cfg = readl(&reg->vidcon2);
cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
EXYNOS_VIDCON2_TVFORMATSEL_MASK |
EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
cfg |= EXYNOS_VIDCON2_WB_DISABLE;
writel(cfg, &reg->vidcon2);
/* set polarity */
cfg = 0;
if (!priv->vl_clkp)
cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
if (!priv->vl_hsp)
cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
if (!priv->vl_vsp)
cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
if (!priv->vl_dp)
cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
writel(cfg, (unsigned int)&reg->vidcon1 + offset);
/* set timing */
cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1);
cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1);
cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1);
writel(cfg, (unsigned int)&reg->vidtcon0 + offset);
cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1);
cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1);
cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1);
writel(cfg, (unsigned int)&reg->vidtcon1 + offset);
/* set lcd size */
cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) |
EXYNOS_VIDTCON2_LINEVAL(priv->vl_row - 1) |
EXYNOS_VIDTCON2_HOZVAL_E(priv->vl_col - 1) |
EXYNOS_VIDTCON2_LINEVAL_E(priv->vl_row - 1);
writel(cfg, (unsigned int)&reg->vidtcon2 + offset);
}
/* set display mode */
cfg = readl(&reg->vidcon0);
cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
writel(cfg, &reg->vidcon0);
/* set par */
exynos_fimd_set_par(priv, priv->win_id);
/* set memory address */
exynos_fimd_set_buffer_address(priv, priv->win_id, plat->base);
/* set buffer size */
cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col *
VNBITS(priv->vl_bpix) / 8) |
EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col *
VNBITS(priv->vl_bpix) / 8) |
EXYNOS_VIDADDR_OFFSIZE(0) |
EXYNOS_VIDADDR_OFFSIZE_E(0);
writel(cfg, (unsigned int)&reg->vidw00add2 +
EXYNOS_BUFFER_SIZE(priv->win_id));
/* set clock */
exynos_fimd_set_clock(priv);
/* set rgb mode to dual lcd. */
exynos_fimd_set_dualrgb(priv, priv->dual_lcd_enabled);
/* display on */
exynos_fimd_lcd_on(priv);
/* window on */
exynos_fimd_window_on(priv, priv->win_id);
exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled);
}
unsigned long exynos_fimd_calc_fbsize(struct exynos_fb_priv *priv)
{
return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8);
}
int exynos_fb_ofdata_to_platdata(struct udevice *dev)
{
struct exynos_fb_priv *priv = dev_get_priv(dev);
unsigned int node = dev->of_offset;
const void *blob = gd->fdt_blob;
fdt_addr_t addr;
addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE) {
debug("Can't get the FIMD base address\n");
return -EINVAL;
}
priv->reg = (struct exynos_fb *)addr;
priv->vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
if (priv->vl_col == 0) {
debug("Can't get XRES\n");
return -ENXIO;
}
priv->vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
if (priv->vl_row == 0) {
debug("Can't get YRES\n");
return -ENXIO;
}
priv->vl_width = fdtdec_get_int(blob, node,
"samsung,vl-width", 0);
priv->vl_height = fdtdec_get_int(blob, node,
"samsung,vl-height", 0);
priv->vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
if (priv->vl_freq == 0) {
debug("Can't get refresh rate\n");
return -ENXIO;
}
if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
priv->vl_clkp = VIDEO_ACTIVE_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
priv->vl_oep = VIDEO_ACTIVE_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
priv->vl_hsp = VIDEO_ACTIVE_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
priv->vl_vsp = VIDEO_ACTIVE_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
priv->vl_dp = VIDEO_ACTIVE_LOW;
priv->vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
if (priv->vl_bpix == 0) {
debug("Can't get bits per pixel\n");
return -ENXIO;
}
priv->vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
if (priv->vl_hspw == 0) {
debug("Can't get hsync width\n");
return -ENXIO;
}
priv->vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
if (priv->vl_hfpd == 0) {
debug("Can't get right margin\n");
return -ENXIO;
}
priv->vl_hbpd = (u_char)fdtdec_get_int(blob, node,
"samsung,vl-hbpd", 0);
if (priv->vl_hbpd == 0) {
debug("Can't get left margin\n");
return -ENXIO;
}
priv->vl_vspw = (u_char)fdtdec_get_int(blob, node,
"samsung,vl-vspw", 0);
if (priv->vl_vspw == 0) {
debug("Can't get vsync width\n");
return -ENXIO;
}
priv->vl_vfpd = fdtdec_get_int(blob, node,
"samsung,vl-vfpd", 0);
if (priv->vl_vfpd == 0) {
debug("Can't get lower margin\n");
return -ENXIO;
}
priv->vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
if (priv->vl_vbpd == 0) {
debug("Can't get upper margin\n");
return -ENXIO;
}
priv->vl_cmd_allow_len = fdtdec_get_int(blob, node,
"samsung,vl-cmd-allow-len", 0);
priv->win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
priv->init_delay = fdtdec_get_int(blob, node,
"samsung,init-delay", 0);
priv->power_on_delay = fdtdec_get_int(blob, node,
"samsung,power-on-delay", 0);
priv->reset_delay = fdtdec_get_int(blob, node,
"samsung,reset-delay", 0);
priv->interface_mode = fdtdec_get_int(blob, node,
"samsung,interface-mode", 0);
priv->mipi_enabled = fdtdec_get_int(blob, node,
"samsung,mipi-enabled", 0);
priv->dp_enabled = fdtdec_get_int(blob, node,
"samsung,dp-enabled", 0);
priv->cs_setup = fdtdec_get_int(blob, node,
"samsung,cs-setup", 0);
priv->wr_setup = fdtdec_get_int(blob, node,
"samsung,wr-setup", 0);
priv->wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
priv->wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
priv->logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
if (priv->logo_on) {
priv->logo_width = fdtdec_get_int(blob, node,
"samsung,logo-width", 0);
priv->logo_height = fdtdec_get_int(blob, node,
"samsung,logo-height", 0);
priv->logo_addr = fdtdec_get_int(blob, node,
"samsung,logo-addr", 0);
}
priv->rgb_mode = fdtdec_get_int(blob, node,
"samsung,rgb-mode", 0);
priv->pclk_name = fdtdec_get_int(blob, node,
"samsung,pclk-name", 0);
priv->sclk_div = fdtdec_get_int(blob, node,
"samsung,sclk-div", 0);
priv->dual_lcd_enabled = fdtdec_get_int(blob, node,
"samsung,dual-lcd-enabled", 0);
return 0;
}
static int exynos_fb_probe(struct udevice *dev)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct exynos_fb_priv *priv = dev_get_priv(dev);
struct udevice *panel, *bridge;
struct udevice *dp;
int ret;
debug("%s: start\n", __func__);
set_system_display_ctrl();
set_lcd_clk();
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(&panel_info);
#endif
exynos_fimd_lcd_init(dev);
ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
printf("LCD panel failed to probe\n");
return ret;
}
if (!panel) {
printf("LCD panel not found\n");
return -ENODEV;
}
ret = uclass_first_device(UCLASS_DISPLAY, &dp);
if (ret) {
debug("%s: Display device error %d\n", __func__, ret);
return ret;
}
if (!dev) {
debug("%s: Display device missing\n", __func__);
return -ENODEV;
}
ret = display_enable(dp, 18, NULL);
if (ret) {
debug("%s: Display enable error %d\n", __func__, ret);
return ret;
}
/* backlight / pwm */
ret = panel_enable_backlight(panel);
if (ret) {
debug("%s: backlight error: %d\n", __func__, ret);
return ret;
}
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
if (!ret)
ret = video_bridge_set_backlight(bridge, 80);
if (ret) {
debug("%s: No video bridge, or no backlight on bridge\n",
__func__);
exynos_pinmux_config(PERIPH_ID_PWM0, 0);
}
uc_priv->xsize = priv->vl_col;
uc_priv->ysize = priv->vl_row;
uc_priv->bpix = priv->vl_bpix;
/* Enable flushing after LCD writes if requested */
video_set_flush_dcache(dev, true);
return 0;
}
static int exynos_fb_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
/* This is the maximum panel size we expect to see */
plat->size = 1920 * 1080 * 2;
return 0;
}
static const struct video_ops exynos_fb_ops = {
};
static const struct udevice_id exynos_fb_ids[] = {
{ .compatible = "samsung,exynos-fimd" },
{ }
};
U_BOOT_DRIVER(exynos_fb) = {
.name = "exynos_fb",
.id = UCLASS_VIDEO,
.of_match = exynos_fb_ids,
.ops = &exynos_fb_ops,
.bind = exynos_fb_bind,
.probe = exynos_fb_probe,
.ofdata_to_platdata = exynos_fb_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct exynos_fb_priv),
};

71
drivers/video/exynos_mipi_dsi.c → drivers/video/exynos/exynos_mipi_dsi.c
View File

@@ -27,13 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct exynos_platform_mipi_dsim *dsim_pd;
#if CONFIG_IS_ENABLED(OF_CONTROL)
static struct mipi_dsim_config dsim_config_dt;
static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
#endif
struct mipi_dsim_ddi {
int bus_id;
struct list_head list;
@@ -178,7 +171,7 @@ static struct mipi_dsim_master_ops master_ops = {
.clear_dsim_frame_done = exynos_mipi_dsi_clear_frame_done,
};
int exynos_mipi_dsi_init(void)
int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd)
{
struct mipi_dsim_device *dsim;
struct mipi_dsim_config *dsim_config;
@@ -239,18 +232,8 @@ int exynos_mipi_dsi_init(void)
return 0;
}
void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
{
if (pd == NULL) {
debug("pd is NULL\n");
return;
}
dsim_pd = pd;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
int exynos_dsim_config_parse_dt(const void *blob)
int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt,
struct mipi_dsim_lcd_device *lcd_dt)
{
int node;
@@ -260,59 +243,59 @@ int exynos_dsim_config_parse_dt(const void *blob)
return -ENODEV;
}
dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
dt->e_interface = fdtdec_get_int(blob, node,
"samsung,dsim-config-e-interface", 0);
dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
dt->e_virtual_ch = fdtdec_get_int(blob, node,
"samsung,dsim-config-e-virtual-ch", 0);
dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
dt->e_pixel_format = fdtdec_get_int(blob, node,
"samsung,dsim-config-e-pixel-format", 0);
dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
dt->e_burst_mode = fdtdec_get_int(blob, node,
"samsung,dsim-config-e-burst-mode", 0);
dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
dt->e_no_data_lane = fdtdec_get_int(blob, node,
"samsung,dsim-config-e-no-data-lane", 0);
dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
dt->e_byte_clk = fdtdec_get_int(blob, node,
"samsung,dsim-config-e-byte-clk", 0);
dsim_config_dt.hfp = fdtdec_get_int(blob, node,
dt->hfp = fdtdec_get_int(blob, node,
"samsung,dsim-config-hfp", 0);
dsim_config_dt.p = fdtdec_get_int(blob, node,
dt->p = fdtdec_get_int(blob, node,
"samsung,dsim-config-p", 0);
dsim_config_dt.m = fdtdec_get_int(blob, node,
dt->m = fdtdec_get_int(blob, node,
"samsung,dsim-config-m", 0);
dsim_config_dt.s = fdtdec_get_int(blob, node,
dt->s = fdtdec_get_int(blob, node,
"samsung,dsim-config-s", 0);
dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
dt->pll_stable_time = fdtdec_get_int(blob, node,
"samsung,dsim-config-pll-stable-time", 0);
dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
dt->esc_clk = fdtdec_get_int(blob, node,
"samsung,dsim-config-esc-clk", 0);
dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
dt->stop_holding_cnt = fdtdec_get_int(blob, node,
"samsung,dsim-config-stop-holding-cnt", 0);
dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
dt->bta_timeout = fdtdec_get_int(blob, node,
"samsung,dsim-config-bta-timeout", 0);
dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
dt->rx_timeout = fdtdec_get_int(blob, node,
"samsung,dsim-config-rx-timeout", 0);
mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
lcd_dt->name = fdtdec_get_config_string(blob,
"samsung,dsim-device-name");
mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
lcd_dt->id = fdtdec_get_int(blob, node,
"samsung,dsim-device-id", 0);
mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
lcd_dt->bus_id = fdtdec_get_int(blob, node,
"samsung,dsim-device-bus_id", 0);
mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
lcd_dt->reverse_panel = fdtdec_get_int(blob, node,
"samsung,dsim-device-reverse-panel", 0);
return 0;
@@ -320,7 +303,12 @@ int exynos_dsim_config_parse_dt(const void *blob)
void exynos_init_dsim_platform_data(vidinfo_t *vid)
{
if (exynos_dsim_config_parse_dt(gd->fdt_blob))
static struct mipi_dsim_config dsim_config_dt;
static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt,
&mipi_lcd_device_dt))
debug("Can't get proper dsim config.\n");
strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
@@ -332,6 +320,5 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid)
mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
dsim_pd = &dsim_platform_data_dt;
vid->dsim_platform_data_dt = &dsim_platform_data_dt;
}
#endif

6
drivers/video/exynos_mipi_dsi_common.c → drivers/video/exynos/exynos_mipi_dsi_common.c
View File

@@ -465,7 +465,7 @@ int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
}
static void convert_to_fb_videomode(struct fb_videomode *mode1,
vidinfo_t *mode2)
struct vidinfo *mode2)
{
mode1->xres = mode2->vl_width;
mode1->yres = mode2->vl_height;
@@ -482,10 +482,10 @@ int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
{
struct exynos_platform_mipi_dsim *dsim_pd;
struct fb_videomode lcd_video;
vidinfo_t *vid;
struct vidinfo *vid;
dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
vid = (vidinfo_t *)dsim_pd->lcd_panel_info;
vid = (struct vidinfo *)dsim_pd->lcd_panel_info;
convert_to_fb_videomode(&lcd_video, vid);

0
drivers/video/exynos_mipi_dsi_common.h → drivers/video/exynos/exynos_mipi_dsi_common.h
View File

0
drivers/video/exynos_mipi_dsi_lowlevel.c → drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
View File

0
drivers/video/exynos_mipi_dsi_lowlevel.h → drivers/video/exynos/exynos_mipi_dsi_lowlevel.h
View File

0
drivers/video/exynos_pwm_bl.c → drivers/video/exynos/exynos_pwm_bl.c
View File

68
drivers/video/exynos_dp_lowlevel.h
View File

@@ -1,68 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EXYNOS_EDP_LOWLEVEL_H
#define _EXYNOS_EDP_LOWLEVEL_H
void exynos_dp_enable_video_bist(unsigned int enable);
void exynos_dp_enable_video_mute(unsigned int enable);
void exynos_dp_reset(void);
void exynos_dp_enable_sw_func(unsigned int enable);
unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable);
unsigned int exynos_dp_get_pll_lock_status(void);
int exynos_dp_init_analog_func(void);
void exynos_dp_init_hpd(void);
void exynos_dp_init_aux(void);
void exynos_dp_config_interrupt(void);
unsigned int exynos_dp_get_plug_in_status(void);
unsigned int exynos_dp_detect_hpd(void);
unsigned int exynos_dp_start_aux_transaction(void);
unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
unsigned char data);
unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
unsigned char *data);
unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
unsigned int exynos_dp_read_bytes_from_dpcd( unsigned int reg_addr,
unsigned int count,
unsigned char data[]);
int exynos_dp_select_i2c_device( unsigned int device_addr,
unsigned int reg_addr);
int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
unsigned int reg_addr, unsigned int *data);
int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
unsigned int reg_addr, unsigned int count,
unsigned char edid[]);
void exynos_dp_reset_macro(void);
void exynos_dp_set_link_bandwidth(unsigned char bwtype);
unsigned char exynos_dp_get_link_bandwidth(void);
void exynos_dp_set_lane_count(unsigned char count);
unsigned int exynos_dp_get_lane_count(void);
unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt);
void exynos_dp_set_lane_pre_emphasis(unsigned int level,
unsigned char lanecnt);
void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
unsigned char lanecnt);
void exynos_dp_set_training_pattern(unsigned int pattern);
void exynos_dp_enable_enhanced_mode(unsigned char enable);
void exynos_dp_enable_scrambling(unsigned int enable);
int exynos_dp_init_video(void);
void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info);
void exynos_dp_set_video_color_format(struct edp_video_info *video_info);
int exynos_dp_config_video_bist(struct edp_device_info *edp_info);
unsigned int exynos_dp_is_slave_video_stream_clock_on(void);
void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
unsigned int n_value);
void exynos_dp_set_video_timing_mode(unsigned int type);
void exynos_dp_enable_video_master(unsigned int enable);
void exynos_dp_start_video(void);
unsigned int exynos_dp_is_video_stream_on(void);
void exynos_dp_set_base_addr(void);
#endif /* _EXYNOS_DP_LOWLEVEL_H */

330
drivers/video/exynos_fb.c
View File

@@ -1,330 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: InKi Dae <inki.dae@samsung.com>
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <lcd.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/system.h>
#include <asm/gpio.h>
#include <asm-generic/errno.h>
#include "exynos_fb.h"
DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
#if CONFIG_IS_ENABLED(OF_CONTROL)
vidinfo_t panel_info = {
/*
* Insert a value here so that we don't end up in the BSS
* Reference: drivers/video/tegra.c
*/
.vl_col = -1,
};
#endif
ushort *configuration_get_cmap(void)
{
#if defined(CONFIG_LCD_LOGO)
return bmp_logo_palette;
#else
return NULL;
#endif
}
static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
{
unsigned long palette_size;
unsigned int fb_size;
fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3);
palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
exynos_fimd_lcd_init_mem((unsigned long)lcdbase,
(unsigned long)fb_size, palette_size);
}
static void exynos_lcd_init(vidinfo_t *vid)
{
exynos_fimd_lcd_init(vid);
/* Enable flushing after LCD writes if requested */
lcd_set_flush_dcache(1);
}
__weak void exynos_cfg_lcd_gpio(void)
{
}
__weak void exynos_backlight_on(unsigned int onoff)
{
}
__weak void exynos_reset_lcd(void)
{
}
__weak void exynos_lcd_power_on(void)
{
}
__weak void exynos_cfg_ldo(void)
{
}
__weak void exynos_enable_ldo(unsigned int onoff)
{
}
__weak void exynos_backlight_reset(void)
{
}
__weak int exynos_lcd_misc_init(vidinfo_t *vid)
{
return 0;
}
static void lcd_panel_on(vidinfo_t *vid)
{
struct gpio_desc pwm_out_gpio;
struct gpio_desc bl_en_gpio;
unsigned int node;
udelay(vid->init_delay);
exynos_backlight_reset();
exynos_cfg_lcd_gpio();
exynos_lcd_power_on();
udelay(vid->power_on_delay);
if (vid->dp_enabled)
exynos_init_dp();
exynos_reset_lcd();
udelay(vid->reset_delay);
exynos_backlight_on(1);
#if CONFIG_IS_ENABLED(OF_CONTROL)
node = fdtdec_next_compatible(gd->fdt_blob, 0,
COMPAT_SAMSUNG_EXYNOS_FIMD);
if (node <= 0) {
debug("FIMD: Can't get device node for FIMD\n");
return;
}
gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
0, &pwm_out_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
&bl_en_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
#endif
exynos_cfg_ldo();
exynos_enable_ldo(1);
if (vid->mipi_enabled)
exynos_mipi_dsi_init();
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
int exynos_lcd_early_init(const void *blob)
{
unsigned int node;
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
if (node <= 0) {
debug("exynos_fb: Can't get device node for fimd\n");
return -ENODEV;
}
panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
if (panel_info.vl_col == 0) {
debug("Can't get XRES\n");
return -ENXIO;
}
panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
if (panel_info.vl_row == 0) {
debug("Can't get YRES\n");
return -ENXIO;
}
panel_info.vl_width = fdtdec_get_int(blob, node,
"samsung,vl-width", 0);
panel_info.vl_height = fdtdec_get_int(blob, node,
"samsung,vl-height", 0);
panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
if (panel_info.vl_freq == 0) {
debug("Can't get refresh rate\n");
return -ENXIO;
}
if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
panel_info.vl_clkp = CONFIG_SYS_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
panel_info.vl_oep = CONFIG_SYS_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
panel_info.vl_hsp = CONFIG_SYS_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
panel_info.vl_vsp = CONFIG_SYS_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
panel_info.vl_dp = CONFIG_SYS_LOW;
panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
if (panel_info.vl_bpix == 0) {
debug("Can't get bits per pixel\n");
return -ENXIO;
}
panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
if (panel_info.vl_hspw == 0) {
debug("Can't get hsync width\n");
return -ENXIO;
}
panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
if (panel_info.vl_hfpd == 0) {
debug("Can't get right margin\n");
return -ENXIO;
}
panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node,
"samsung,vl-hbpd", 0);
if (panel_info.vl_hbpd == 0) {
debug("Can't get left margin\n");
return -ENXIO;
}
panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node,
"samsung,vl-vspw", 0);
if (panel_info.vl_vspw == 0) {
debug("Can't get vsync width\n");
return -ENXIO;
}
panel_info.vl_vfpd = fdtdec_get_int(blob, node,
"samsung,vl-vfpd", 0);
if (panel_info.vl_vfpd == 0) {
debug("Can't get lower margin\n");
return -ENXIO;
}
panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
if (panel_info.vl_vbpd == 0) {
debug("Can't get upper margin\n");
return -ENXIO;
}
panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node,
"samsung,vl-cmd-allow-len", 0);
panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
panel_info.init_delay = fdtdec_get_int(blob, node,
"samsung,init-delay", 0);
panel_info.power_on_delay = fdtdec_get_int(blob, node,
"samsung,power-on-delay", 0);
panel_info.reset_delay = fdtdec_get_int(blob, node,
"samsung,reset-delay", 0);
panel_info.interface_mode = fdtdec_get_int(blob, node,
"samsung,interface-mode", 0);
panel_info.mipi_enabled = fdtdec_get_int(blob, node,
"samsung,mipi-enabled", 0);
panel_info.dp_enabled = fdtdec_get_int(blob, node,
"samsung,dp-enabled", 0);
panel_info.cs_setup = fdtdec_get_int(blob, node,
"samsung,cs-setup", 0);
panel_info.wr_setup = fdtdec_get_int(blob, node,
"samsung,wr-setup", 0);
panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
if (panel_info.logo_on) {
panel_info.logo_width = fdtdec_get_int(blob, node,
"samsung,logo-width", 0);
panel_info.logo_height = fdtdec_get_int(blob, node,
"samsung,logo-height", 0);
panel_info.logo_addr = fdtdec_get_int(blob, node,
"samsung,logo-addr", 0);
}
panel_info.rgb_mode = fdtdec_get_int(blob, node,
"samsung,rgb-mode", 0);
panel_info.pclk_name = fdtdec_get_int(blob, node,
"samsung,pclk-name", 0);
panel_info.sclk_div = fdtdec_get_int(blob, node,
"samsung,sclk-div", 0);
panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node,
"samsung,dual-lcd-enabled", 0);
return 0;
}
#endif
void lcd_ctrl_init(void *lcdbase)
{
set_system_display_ctrl();
set_lcd_clk();
#if CONFIG_IS_ENABLED(OF_CONTROL)
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(&panel_info);
#endif
exynos_lcd_misc_init(&panel_info);
#else
/* initialize parameters which is specific to panel. */
init_panel_info(&panel_info);
#endif
panel_width = panel_info.vl_width;
panel_height = panel_info.vl_height;
exynos_lcd_init_mem(lcdbase, &panel_info);
exynos_lcd_init(&panel_info);
}
void lcd_enable(void)
{
if (panel_info.logo_on) {
memset((void *) gd->fb_base, 0, panel_width * panel_height *
(NBITS(panel_info.vl_bpix) >> 3));
}
lcd_panel_on(&panel_info);
}
/* dummy function */
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
{
return;
}

41
drivers/video/exynos_fb.h
View File

@@ -1,41 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: InKi Dae <inki.dae@samsung.com>
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EXYNOS_FB_H_
#define _EXYNOS_FB_H_
#include <asm/arch/fb.h>
#define MAX_CLOCK (86 * 1000000)
enum exynos_cpu_auto_cmd_rate {
DISABLE_AUTO_FRM,
PER_TWO_FRM,
PER_FOUR_FRM,
PER_SIX_FRM,
PER_EIGHT_FRM,
PER_TEN_FRM,
PER_TWELVE_FRM,
PER_FOURTEEN_FRM,
PER_SIXTEEN_FRM,
PER_EIGHTEEN_FRM,
PER_TWENTY_FRM,
PER_TWENTY_TWO_FRM,
PER_TWENTY_FOUR_FRM,
PER_TWENTY_SIX_FRM,
PER_TWENTY_EIGHT_FRM,
PER_THIRTY_FRM,
};
void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
unsigned long palette_size);
void exynos_fimd_lcd_init(vidinfo_t *vid);
unsigned long exynos_fimd_calc_fbsize(void);
#endif

409
drivers/video/exynos_fimd.c
View File

@@ -1,409 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* Author: InKi Dae <inki.dae@samsung.com>
* Author: Donghwa Lee <dh09.lee@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <lcd.h>
#include <div64.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include "exynos_fb.h"
DECLARE_GLOBAL_DATA_PTR;
static unsigned long *lcd_base_addr;
static vidinfo_t *pvid;
static struct exynos_fb *fimd_ctrl;
void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
u_long palette_size)
{
lcd_base_addr = (unsigned long *)screen_base;
}
static void exynos_fimd_set_dualrgb(unsigned int enabled)
{
unsigned int cfg = 0;
if (enabled) {
cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
EXYNOS_DUALRGB_VDEN_EN_ENABLE;
/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
EXYNOS_DUALRGB_MAIN_CNT(0);
}
writel(cfg, &fimd_ctrl->dualrgb);
}
static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
{
unsigned int cfg = 0;
if (enabled)
cfg = EXYNOS_DP_CLK_ENABLE;
writel(cfg, &fimd_ctrl->dp_mie_clkcon);
}
static void exynos_fimd_set_par(unsigned int win_id)
{
unsigned int cfg = 0;
/* set window control */
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
/* DATAPATH is DMA */
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
/* dma burst is 16 */
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
switch (pvid->vl_bpix) {
case 4:
cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
break;
default:
cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
break;
}
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
/* set window position to x=0, y=0*/
cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
EXYNOS_VIDOSD(win_id));
cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
EXYNOS_VIDOSD_RIGHT_X_E(1) |
EXYNOS_VIDOSD_BOTTOM_Y_E(0);
writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
EXYNOS_VIDOSD(win_id));
/* set window size for window0*/
cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
EXYNOS_VIDOSD(win_id));
}
static void exynos_fimd_set_buffer_address(unsigned int win_id)
{
unsigned long start_addr, end_addr;
start_addr = (unsigned long)lcd_base_addr;
end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
pvid->vl_row);
writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
EXYNOS_BUFFER_OFFSET(win_id));
writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
EXYNOS_BUFFER_OFFSET(win_id));
}
static void exynos_fimd_set_clock(vidinfo_t *pvid)
{
unsigned int cfg = 0, div = 0, remainder, remainder_div;
unsigned long pixel_clock;
unsigned long long src_clock;
if (pvid->dual_lcd_enabled) {
pixel_clock = pvid->vl_freq *
(pvid->vl_hspw + pvid->vl_hfpd +
pvid->vl_hbpd + pvid->vl_col / 2) *
(pvid->vl_vspw + pvid->vl_vfpd +
pvid->vl_vbpd + pvid->vl_row);
} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
pixel_clock = pvid->vl_freq *
pvid->vl_width * pvid->vl_height *
(pvid->cs_setup + pvid->wr_setup +
pvid->wr_act + pvid->wr_hold + 1);
} else {
pixel_clock = pvid->vl_freq *
(pvid->vl_hspw + pvid->vl_hfpd +
pvid->vl_hbpd + pvid->vl_col) *
(pvid->vl_vspw + pvid->vl_vfpd +
pvid->vl_vbpd + pvid->vl_row);
}
cfg = readl(&fimd_ctrl->vidcon0);
cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
EXYNOS_VIDCON0_CLKDIR_MASK);
cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
src_clock = (unsigned long long) get_lcd_clk();
/* get quotient and remainder. */
remainder = do_div(src_clock, pixel_clock);
div = src_clock;
remainder *= 10;
remainder_div = remainder / pixel_clock;
/* round about one places of decimals. */
if (remainder_div >= 5)
div++;
/* in case of dual lcd mode. */
if (pvid->dual_lcd_enabled)
div--;
cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
writel(cfg, &fimd_ctrl->vidcon0);
}
void exynos_set_trigger(void)
{
unsigned int cfg = 0;
cfg = readl(&fimd_ctrl->trigcon);
cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
writel(cfg, &fimd_ctrl->trigcon);
}
int exynos_is_i80_frame_done(void)
{
unsigned int cfg = 0;
int status;
cfg = readl(&fimd_ctrl->trigcon);
/* frame done func is valid only when TRIMODE[0] is set to 1. */
status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
EXYNOS_I80STATUS_TRIG_DONE;
return status;
}
static void exynos_fimd_lcd_on(void)
{
unsigned int cfg = 0;
/* display on */
cfg = readl(&fimd_ctrl->vidcon0);
cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
writel(cfg, &fimd_ctrl->vidcon0);
}
static void exynos_fimd_window_on(unsigned int win_id)
{
unsigned int cfg = 0;
/* enable window */
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
cfg = readl(&fimd_ctrl->winshmap);
cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
writel(cfg, &fimd_ctrl->winshmap);
}
void exynos_fimd_lcd_off(void)
{
unsigned int cfg = 0;
cfg = readl(&fimd_ctrl->vidcon0);
cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
writel(cfg, &fimd_ctrl->vidcon0);
}
void exynos_fimd_window_off(unsigned int win_id)
{
unsigned int cfg = 0;
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
cfg = readl(&fimd_ctrl->winshmap);
cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
writel(cfg, &fimd_ctrl->winshmap);
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
/*
* The reset value for FIMD SYSMMU register MMU_CTRL is 3
* on Exynos5420 and newer versions.
* This means FIMD SYSMMU is on by default on Exynos5420
* and newer versions.
* Since in u-boot we don't use SYSMMU, we should disable
* those FIMD SYSMMU.
* Note that there are 2 SYSMMU for FIMD: m0 and m1.
* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
* We disable both of them here.
*/
void exynos_fimd_disable_sysmmu(void)
{
u32 *sysmmufimd;
unsigned int node;
int node_list[2];
int count;
int i;
count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
for (i = 0; i < count; i++) {
node = node_list[i];
if (node <= 0) {
debug("Can't get device node for fimd sysmmu\n");
return;
}
sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
if (!sysmmufimd) {
debug("Can't get base address for sysmmu fimdm0");
return;
}
writel(0x0, sysmmufimd);
}
}
#endif
void exynos_fimd_lcd_init(vidinfo_t *vid)
{
unsigned int cfg = 0, rgb_mode;
unsigned int offset;
#if CONFIG_IS_ENABLED(OF_CONTROL)
unsigned int node;
node = fdtdec_next_compatible(gd->fdt_blob,
0, COMPAT_SAMSUNG_EXYNOS_FIMD);
if (node <= 0)
debug("exynos_fb: Can't get device node for fimd\n");
fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob,
node, "reg");
if (fimd_ctrl == NULL)
debug("Can't get the FIMD base address\n");
if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
exynos_fimd_disable_sysmmu();
#else
fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
#endif
offset = exynos_fimd_get_base_offset();
/* store panel info to global variable */
pvid = vid;
rgb_mode = vid->rgb_mode;
if (vid->interface_mode == FIMD_RGB_INTERFACE) {
cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
writel(cfg, &fimd_ctrl->vidcon0);
cfg = readl(&fimd_ctrl->vidcon2);
cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
EXYNOS_VIDCON2_TVFORMATSEL_MASK |
EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
cfg |= EXYNOS_VIDCON2_WB_DISABLE;
writel(cfg, &fimd_ctrl->vidcon2);
/* set polarity */
cfg = 0;
if (!pvid->vl_clkp)
cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
if (!pvid->vl_hsp)
cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
if (!pvid->vl_vsp)
cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
if (!pvid->vl_dp)
cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
/* set timing */
cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
/* set lcd size */
cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
}
/* set display mode */
cfg = readl(&fimd_ctrl->vidcon0);
cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
writel(cfg, &fimd_ctrl->vidcon0);
/* set par */
exynos_fimd_set_par(pvid->win_id);
/* set memory address */
exynos_fimd_set_buffer_address(pvid->win_id);
/* set buffer size */
cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
EXYNOS_VIDADDR_OFFSIZE(0) |
EXYNOS_VIDADDR_OFFSIZE_E(0);
writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
EXYNOS_BUFFER_SIZE(pvid->win_id));
/* set clock */
exynos_fimd_set_clock(pvid);
/* set rgb mode to dual lcd. */
exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
/* display on */
exynos_fimd_lcd_on();
/* window on */
exynos_fimd_window_on(pvid->win_id);
exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
}
unsigned long exynos_fimd_calc_fbsize(void)
{
return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
}

4
drivers/video/s6e8ax0.c
View File

@@ -9,8 +9,8 @@
#include <common.h>
#include <asm/arch/mipi_dsim.h>
#include "exynos_mipi_dsi_lowlevel.h"
#include "exynos_mipi_dsi_common.h"
#include "exynos/exynos_mipi_dsi_lowlevel.h"
#include "exynos/exynos_mipi_dsi_common.h"
static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
{

2
drivers/video/simple_panel.c
View File

@@ -88,6 +88,8 @@ static const struct panel_ops simple_panel_ops = {
static const struct udevice_id simple_panel_ids[] = {
{ .compatible = "simple-panel" },
{ .compatible = "auo,b133xtn01" },
{ .compatible = "auo,b116xw03" },
{ .compatible = "auo,b133htn01" },
{ }
};