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armv8:fsl-layerscape: Add support for Chassis 3.2

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NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.

Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Priyanka Jain
2018-10-29 09:11:29 +00:00
committed by York Sun
parent db1e3df7ce
commit d6fdec211f
5 changed files with 68 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@@ -180,6 +180,9 @@ config FSL_LSCH2
config FSL_LSCH3
bool
config NXP_LSCH3_2
bool
config FSL_MC_ENET
bool "Management Complex network"
depends on ARCH_LS2080A || ARCH_LS1088A

18
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@@ -120,6 +120,13 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#ifdef CONFIG_SYS_FSL_DRAM_BASE3
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
CONFIG_SYS_FSL_CCSR_SIZE,
@@ -266,6 +273,13 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#ifdef CONFIG_SYS_FSL_DRAM_BASE3
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
CONFIG_SYS_FSL_BOOTROM_SIZE,
@@ -595,13 +609,13 @@ enum boot_src __get_boot_src(u32 porsr1)
{
enum boot_src src = BOOT_SOURCE_RESERVED;
u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
#if !defined(CONFIG_FSL_LSCH3_2)
#if !defined(CONFIG_NXP_LSCH3_2)
u32 val;
#endif
debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
#if defined(CONFIG_FSL_LSCH3)
#if defined(CONFIG_FSL_LSCH3_2)
#if defined(CONFIG_NXP_LSCH3_2)
switch (rcw_src) {
case RCW_SRC_SDHC1_VAL:
src = BOOT_SOURCE_SD_MMC;

27
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 Normal file
View File

@@ -0,0 +1,27 @@
#
# Copyright 2018 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
NXP LayerScape with Chassis Generation 3.2
This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2
for example LX2160A.
This architecture is enhancement over Chassis Generation 3 with
few differences mentioned below
1)DDR Layout
============
Entire DDR region splits into three regions.
- Region 1 is at address 0x8000_0000 to 0xffff_ffff.
- Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff,
- Region 3 is at address 0x60_0000_0000 to the top of memory,
for example 140GB, 0x63_7fff_ffff.
All DDR memory is marked as cache-enabled.
2)IFC is removed
3)Number of I2C controllers increased to 8