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ARM: uniphier: change the external bus address mapping

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In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
 0x00000000 - 0x0fffffff
 0x40000000 - 0x4fffffff
are both mapped to the external bus (also called system bus),
so either was OK.

In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is
assigned for the serial NOR interface.

Going forward, use the latter for the external bus.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Masahiro Yamada 2015-09-11 20:17:47 +09:00
parent 4ef542efd5
commit d5ed8c5727
5 changed files with 25 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
View File

@ -30,18 +30,18 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x03efffff: memory bank (31MB)
* 0x03f00000-0x03ffffff: peripherals (1MB)
* 0x40000000-0x41ffffff: mask ROM
* 0x42000000-0x43efffff: memory bank (31MB)
* 0x43f00000-0x43ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);

12
arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
View File

@ -23,18 +23,18 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x03efffff: memory bank (31MB)
* 0x03f00000-0x03ffffff: peripherals (1MB)
* 0x40000000-0x41ffffff: mask ROM
* 0x42000000-0x43efffff: memory bank (31MB)
* 0x43f00000-0x43ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);

12
arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
View File

@ -24,18 +24,18 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
* 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
* 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
* 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x03efffff: memory bank (31MB)
* 0x03f00000-0x03ffffff: peripherals (1MB)
* 0x40000000-0x41ffffff: mask ROM
* 0x42000000-0x43efffff: memory bank (31MB)
* 0x43f00000-0x43ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);

2
arch/arm/mach-uniphier/support_card.c
View File

@ -103,7 +103,7 @@ static int mem_is_flash(const struct memory_bank *mem)
/* {address, size} */
static const struct memory_bank memory_banks[] = {
{0x02000000, 0x01f00000},
{0x42000000, 0x01f00000},
};
static const struct memory_bank

7
include/configs/uniphier.h
View File

@ -62,7 +62,7 @@
/*
* Support card address map
*/
#define CONFIG_SUPPORT_CARD_BASE 0x03f00000
#define CONFIG_SUPPORT_CARD_BASE 0x43f00000
#define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
#define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
#define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
@ -240,6 +240,7 @@
"fit_addr_r=0x84100000\0" \
"fit_size=0x00f00000\0" \
"norboot=run add_default_bootargs &&" \
"setexpr fit_addr $nor_base + $fit_addr &&" \
"bootm $fit_addr\0" \
"nandboot=run add_default_bootargs &&" \
"nand read $fit_addr_r $fit_addr $fit_size &&" \
@ -262,6 +263,9 @@
"ramdisk_size=0x00600000\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \
"norboot=run add_default_bootargs &&" \
"setexpr kernel_addr $nor_base + $kernel_addr &&" \
"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
"setexpr fdt_addr $nor_base + $fdt_addr &&" \
"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
"nandboot=run add_default_bootargs &&" \
"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
@ -278,6 +282,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"verify=n\0" \
"norbase=0x42000000\0" \
"nandupdate=nand erase 0 0x00100000 &&" \
"tftpboot u-boot-spl-dtb.bin &&" \
"nand write $loadaddr 0 0x00010000 &&" \