pinctrl: rmobile: Add pinconf to Renesas RCar pincontrol driver
Add pinconf support to the PFC driver, so that it can handle DT props bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Nobuhiro Iwamatsu
parent
c322d4b72b
commit
d52132c320
@ -477,6 +477,188 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector
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done:
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return ret;
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}
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#if CONFIG_IS_ENABLED(PINCONF)
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static const struct pinconf_param sh_pfc_pinconf_params[] = {
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
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{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
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{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
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{ "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
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};
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static void __iomem *
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sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
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unsigned int *offset, unsigned int *size)
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{
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const struct pinmux_drive_reg_field *field;
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const struct pinmux_drive_reg *reg;
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unsigned int i;
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for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
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for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
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field = ®->fields[i];
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if (field->size && field->pin == pin) {
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*offset = field->offset;
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*size = field->size;
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return (void __iomem *)(uintptr_t)reg->reg;
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}
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}
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}
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return NULL;
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}
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static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
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unsigned int pin, u16 strength)
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{
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unsigned int offset;
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unsigned int size;
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unsigned int step;
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void __iomem *reg;
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void __iomem *unlock_reg =
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(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
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u32 val;
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reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
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if (!reg)
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return -EINVAL;
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step = size == 2 ? 6 : 3;
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if (strength < step || strength > 24)
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return -EINVAL;
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/* Convert the value from mA based on a full drive strength value of
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* 24mA. We can make the full value configurable later if needed.
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*/
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strength = strength / step - 1;
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val = sh_pfc_read_raw_reg(reg, 32);
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val &= ~GENMASK(offset + size - 1, offset);
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val |= strength << offset;
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if (unlock_reg)
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sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
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sh_pfc_write_raw_reg(reg, 32, val);
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return 0;
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}
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/* Check whether the requested parameter is supported for a pin. */
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static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
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unsigned int param)
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{
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int idx = sh_pfc_get_pin_index(pfc, _pin);
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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return pin->configs &
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(SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
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case PIN_CONFIG_BIAS_PULL_UP:
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return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
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case PIN_CONFIG_DRIVE_STRENGTH:
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return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
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case PIN_CONFIG_POWER_SOURCE:
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return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
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default:
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return false;
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}
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}
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static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
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unsigned int param, unsigned int arg)
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{
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struct sh_pfc *pfc = pmx->pfc;
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void __iomem *pocctrl;
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void __iomem *unlock_reg =
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(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
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u32 addr, val;
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int bit, ret;
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if (!sh_pfc_pinconf_validate(pfc, _pin, param))
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return -ENOTSUPP;
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switch (param) {
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_DISABLE:
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if (!pfc->info->ops || !pfc->info->ops->set_bias)
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return -ENOTSUPP;
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pfc->info->ops->set_bias(pfc, _pin, param);
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
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if (ret < 0)
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return ret;
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break;
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case PIN_CONFIG_POWER_SOURCE:
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if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
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return -ENOTSUPP;
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bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
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if (bit < 0) {
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printf("invalid pin %#x", _pin);
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return bit;
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}
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if (arg != 1800 && arg != 3300)
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return -EINVAL;
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pocctrl = (void __iomem *)(uintptr_t)addr;
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val = sh_pfc_read_raw_reg(pocctrl, 32);
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if (arg == 3300)
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val |= BIT(bit);
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else
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val &= ~BIT(bit);
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if (unlock_reg)
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sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
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sh_pfc_write_raw_reg(pocctrl, 32, val);
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static int sh_pfc_pinconf_group_set(struct udevice *dev,
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unsigned int group_selector,
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unsigned int param, unsigned int arg)
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{
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struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
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struct sh_pfc_pinctrl *pmx = &priv->pmx;
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struct sh_pfc *pfc = &priv->pfc;
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const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
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unsigned int i;
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for (i = 0; i < grp->nr_pins; i++)
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sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
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return 0;
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}
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#endif
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static struct pinctrl_ops sh_pfc_pinctrl_ops = {
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.get_pins_count = sh_pfc_pinctrl_get_pins_count,
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@ -486,6 +668,11 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = {
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.get_functions_count = sh_pfc_pinctrl_get_functions_count,
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.get_function_name = sh_pfc_pinctrl_get_function_name,
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#if CONFIG_IS_ENABLED(PINCONF)
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.pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
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.pinconf_params = sh_pfc_pinconf_params,
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.pinconf_group_set = sh_pfc_pinconf_group_set,
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#endif
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.pinmux_group_set = sh_pfc_pinctrl_group_set,
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.set_state = pinctrl_generic_set_state,
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};
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