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ARM: OMAP5: USB: Add OMAP5 common USB EHCI information

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* Enable the OMAP5 EHCI host clocks
* Add OMAP5 EHCI register definitions
* Add OMAP5 ES2 host revision

Signed-off-by: Dan Murphy <dmurphy@ti.com>
This commit is contained in:
Dan Murphy 2013-08-01 14:05:57 -05:00 committed by Marek Vasut
parent 5a7bd38437
commit d3d037ae18
4 changed files with 86 additions and 2 deletions
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17
arch/arm/include/asm/arch-omap5/clock.h
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@ -149,6 +149,23 @@
/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OPTFCLKEN_FUNC48M_CLK (1 << 15)
#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14)
#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13)
#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12)
#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11)
#define OPTFCLKEN_UTMI_P3_CLK (1 << 10)
#define OPTFCLKEN_UTMI_P2_CLK (1 << 9)
#define OPTFCLKEN_UTMI_P1_CLK (1 << 8)
#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7)
#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6)
/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8)
#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9)
#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10)
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)

43
arch/arm/include/asm/arch-omap5/ehci.h Normal file
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@ -0,0 +1,43 @@
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _EHCI_H
#define _EHCI_H
#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00)
#define OMAP_UHH_BASE (OMAP54XX_L4_CORE_BASE + 0x64000)
#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000)
/* TLL Register Set */
#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1
#define OMAP_UHH_SYSCONFIG_SOFTRESET 1
#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2)
#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2)
#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4)
#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \
OMAP_UHH_SYSCONFIG_NOSTDBY)
#endif /* _EHCI_H */

2
arch/arm/include/asm/ehci-omap.h
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@ -42,6 +42,7 @@ enum usbhs_omap_port_mode {
/* Values of UHH_REVISION - Note: these are not given in the TRM */
#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
#define OMAP_USBHS_REV2_1 0x50700101 /* OMAP5 */
/* UHH Register Set */
#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
@ -60,6 +61,7 @@ enum usbhs_omap_port_mode {
#define OMAP_P2_MODE_CLEAR (3 << 18)
#define OMAP_P2_MODE_TLL (1 << 18)
#define OMAP_P2_MODE_HSIC (3 << 18)
#define OMAP_P3_MODE_CLEAR (3 << 20)
#define OMAP_P3_MODE_HSIC (3 << 20)
/* EHCI Register Set */

26
drivers/usb/host/ehci-omap.c
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@ -96,7 +96,8 @@ inline int __board_usb_init(void)
int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
/* controls PHY(s) reset signal(s) */
static inline void omap_ehci_phy_reset(int on, int delay)
{
@ -115,6 +116,10 @@ static inline void omap_ehci_phy_reset(int on, int delay)
gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
#endif
#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
#endif
/* Hold the PHY in RESET for enough time till DIR is high */
/* Refer: ISSUE1 */
@ -198,10 +203,27 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
else
setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
} else if (rev == OMAP_USBHS_REV2) {
clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
/* Clear port mode fields for PHY mode*/
/* Clear port mode fields for PHY mode */
if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
setbits_le32(&reg, OMAP_P1_MODE_HSIC);
if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
setbits_le32(&reg, OMAP_P2_MODE_HSIC);
} else if (rev == OMAP_USBHS_REV2_1) {
clrsetbits_le32(&reg,
(OMAP_P1_MODE_CLEAR |
OMAP_P2_MODE_CLEAR |
OMAP_P3_MODE_CLEAR),
OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
/* Clear port mode fields for PHY mode */
if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
setbits_le32(&reg, OMAP_P1_MODE_HSIC);