mvgbe: add support for orion5x GbE controller
Add definitions and initialization in orion5x for mvgbe. Add orion5x in mvgbe SoC includes. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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@ -268,3 +268,11 @@ int arch_misc_init(void)
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return 0;
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return 0;
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}
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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#endif /* CONFIG_ARCH_MISC_INIT */
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#ifdef CONFIG_MVGBE
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int cpu_eth_init(bd_t *bis)
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{
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mvgbe_initialize(bis);
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return 0;
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}
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#endif
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@ -60,8 +60,10 @@
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#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
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#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
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#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
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#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
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#define MVGBE0_BASE KW_EGIGA0_BASE
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/* Kirkwood GbE controller has two ports */
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#define MVGBE1_BASE KW_EGIGA1_BASE
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#define MAX_MVGBE_DEVS 2
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#define MVGBE0_BASE KW_EGIGA0_BASE
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#define MVGBE1_BASE KW_EGIGA1_BASE
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#if defined (CONFIG_KW88F6281)
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#if defined (CONFIG_KW88F6281)
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#include <asm/arch/kw88f6281.h>
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#include <asm/arch/kw88f6281.h>
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@ -56,6 +56,10 @@
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#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
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#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
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#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
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#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
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/* Orion5x GbE controller has a single port */
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#define MAX_MVGBE_DEVS 1
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#define MVGBE0_BASE ORION5X_EGIGA_BASE
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#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
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#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
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/* include here SoC variants. 5181, 5281, 6183 should go here when
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/* include here SoC variants. 5181, 5281, 6183 should go here when
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@ -38,6 +38,8 @@
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#if defined(CONFIG_KIRKWOOD)
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#if defined(CONFIG_KIRKWOOD)
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/kirkwood.h>
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#elif defined(CONFIG_ORION5X)
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#include <asm/arch/orion5x.h>
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#endif
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#endif
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#include "mvgbe.h"
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#include "mvgbe.h"
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@ -28,8 +28,6 @@
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#ifndef __MVGBE_H__
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#ifndef __MVGBE_H__
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#define __MVGBE_H__
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#define __MVGBE_H__
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#define MAX_MVGBE_DEVS 2 /*controller has two ports */
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/* PHY_BASE_ADR is board specific and can be configured */
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/* PHY_BASE_ADR is board specific and can be configured */
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#if defined (CONFIG_PHY_BASE_ADR)
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#if defined (CONFIG_PHY_BASE_ADR)
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#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
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#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
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