OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Manikandan Pillai <mani.pillai@ti.com>
This commit is contained in:
Manikandan Pillai
Wolfgang Denk
parent
9d5e4d3681
commit
d3a513c23b
@ -36,8 +36,6 @@
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#include <asm/io.h>
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#include <asm/proc-armv/ptrace.h>
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#define TIMER_LOAD_VAL 0
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#ifdef CONFIG_USE_IRQ
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/* enable IRQ interrupts */
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void enable_interrupts(void)
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@ -169,7 +167,17 @@ static ulong timestamp;
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static ulong lastinc;
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static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
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/* nothing really to do with interrupts, just starts up a counter. */
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/*
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* Nothing really to do with interrupts, just starts up a counter.
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* We run the counter with 13MHz, divided by 8, resulting in timer
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* frequency of 1.625MHz. With 32bit counter register, counter
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* overflows in ~44min
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*/
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/* 13MHz / 8 = 1.625MHz */
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#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
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#define TIMER_LOAD_VAL 0xffffffff
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int interrupt_init(void)
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{
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/* start the counter ticking up, reload value on overflow */
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@ -201,81 +209,44 @@ void set_timer(ulong t)
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timestamp = t;
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}
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/* delay x useconds AND perserve advance timstamp value */
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/* delay x useconds */
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void udelay(unsigned long usec)
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{
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ulong tmo, tmp;
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long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
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unsigned long now, last = readl(&timer_base->tcrr);
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/* if "big" number, spread normalization to seconds */
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if (usec >= 1000) {
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/* if "big" number, spread normalization to seconds */
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tmo = usec / 1000;
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/* find number of "ticks" to wait to achieve target */
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tmo *= CONFIG_SYS_HZ;
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tmo /= 1000; /* finish normalize. */
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} else {/* else small number, don't kill it prior to HZ multiply */
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= (1000 * 1000);
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while (tmo > 0) {
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now = readl(&timer_base->tcrr);
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if (last > now) /* count up timer overflow */
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tmo -= TIMER_LOAD_VAL - last + now;
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else
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tmo -= now - last;
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last = now;
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}
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tmp = get_timer(0); /* get current timestamp */
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/* if setting this forward will roll time stamp */
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if ((tmo + tmp + 1) < tmp)
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/* reset "advancing" timestamp to 0, set lastinc value */
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reset_timer_masked();
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else
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tmo += tmp; /* else, set advancing stamp wake up time */
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while (get_timer_masked() < tmo) /* loop till event */
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/*NOP*/;
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}
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void reset_timer_masked(void)
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{
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/* reset time, capture current incrementer value time */
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lastinc = readl(&timer_base->tcrr);
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lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
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timestamp = 0; /* start "advancing" time stamp from 0 */
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}
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ulong get_timer_masked(void)
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{
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ulong now = readl(&timer_base->tcrr); /* current tick value */
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/* current tick value */
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ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
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if (now >= lastinc) /* normal mode (non roll) */
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/* move stamp fordward with absoulte diff ticks */
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timestamp += (now - lastinc);
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else /* we have rollover of incrementer */
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timestamp += (0xFFFFFFFF - lastinc) + now;
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timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
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- lastinc) + now;
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lastinc = now;
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return timestamp;
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}
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/* waits specified delay value and resets timestamp */
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void udelay_masked(unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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signed long diff;
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/* if "big" number, spread normalization to seconds */
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if (usec >= 1000) {
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/* start to normalize for usec to ticks per sec */
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tmo = usec / 1000;
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/* find number of "ticks" to wait to achieve target */
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tmo *= CONFIG_SYS_HZ;
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tmo /= 1000; /* finish normalize. */
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} else { /* else small number, */
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/* don't kill it prior to HZ multiply */
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= (1000 * 1000);
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}
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endtime = get_timer_masked() + tmo;
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do {
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ulong now = get_timer_masked();
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diff = endtime - now;
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} while (diff >= 0);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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@ -291,7 +262,5 @@ unsigned long long get_ticks(void)
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*/
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ulong get_tbclk(void)
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{
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ulong tbclk;
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tbclk = CONFIG_SYS_HZ;
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return tbclk;
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return CONFIG_SYS_HZ;
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}
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@ -217,12 +217,13 @@
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/* load address */
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/*
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -209,12 +209,13 @@
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/* address */
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/*
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -201,14 +201,14 @@
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
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/* address */
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/*
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -206,12 +206,13 @@
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/* address */
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/*
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Stack sizes
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@ -226,12 +226,13 @@
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/* load address */
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/*
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Stack sizes
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