net: phy: micrel: Separate KSZ9000 drivers from KSZ8000 drivers
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they share the same ID. Drivers for bothe PHYs cannot safely coexist, so the solution was to use #ifdefs to select between the two drivers. As a result KSZ9031, which has a unique ID, is now caught in the crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031 will not function properly, as some essential configuration code is ifdef'd-out. To prevent such situations, move the KSZ9000 drivers to a separate file, and place them under a separate Kconfig option. While it is possible to enable both KSZ8000 and KSZ9000 drivers at the same time, the assumption is that it is highly unlikely for a system to contain both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers will be enabled at any given time. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Alexandru Gagniuc
Joe Hershberger
parent
cb543d30df
commit
d397f7c45b
@ -69,6 +69,7 @@ if PHY_MICREL
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config PHY_MICREL_KSZ9021
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bool "Micrel KSZ9021 family support"
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select PHY_GIGE
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select PHY_MICREL_KSZ90X1
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help
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Enable support for the Micrel KSZ9021 GbE PHY family. If
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enabled, the extended register read/write for KSZ9021 PHYs
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@ -80,9 +81,12 @@ config PHY_MICREL_KSZ9021
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KSZ8921BL, so enabling this option disables support for the
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KSZ8721BL.
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Deprecated. Use PHY_MICREL_KSZ90X1 instead.
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config PHY_MICREL_KSZ9031
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bool "Micrel KSZ9031 family support"
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select PHY_GIGE
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select PHY_MICREL_KSZ90X1
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help
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Enable support for the Micrel KSZ9031 GbE PHY family. If
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enabled, the extended register read/write for KSZ9021 PHYs
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@ -90,6 +94,32 @@ config PHY_MICREL_KSZ9031
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delays configured in the device tree will be applied to the
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PHY during initialisatioin.
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Deprecated. Use PHY_MICREL_KSZ90X1 instead.
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config PHY_MICREL_KSZ90X1
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bool "Micrel KSZ90x1 family support"
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select PHY_GIGE
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help
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Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
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enabled, the extended register read/write for KSZ90x1 PHYs
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is supported through the 'mdio' command and any RGMII signal
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delays configured in the device tree will be applied to the
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PHY during initialization.
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This should not be enabled at the same time with PHY_MICREL_KSZ8XXX
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as the KSZ9021 and KS8721 share the same ID.
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config PHY_MICREL_KSZ8XXX
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bool "Micrel KSZ8xxx family support"
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default y if !PHY_MICREL_KSZ90X1
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help
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Enable support for the 8000 series GbE PHYs manufactured by Micrel
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(now a part of Microchip). This includes drivers for the KSZ804,
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KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
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This should not be enabled at the same time with PHY_MICREL_KSZ90X1
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as the KSZ9021 and KS8721 share the same ID.
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endif # PHY_MICREL
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config PHY_MSCC
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@ -19,7 +19,8 @@ obj-$(CONFIG_PHY_DAVICOM) += davicom.o
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obj-$(CONFIG_PHY_ET1011C) += et1011c.o
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obj-$(CONFIG_PHY_LXT) += lxt.o
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obj-$(CONFIG_PHY_MARVELL) += marvell.o
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obj-$(CONFIG_PHY_MICREL) += micrel.o
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obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
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obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
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obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
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obj-$(CONFIG_PHY_REALTEK) += realtek.o
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obj-$(CONFIG_PHY_SMSC) += smsc.o
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@ -365,7 +365,8 @@ static int ksz9021_config(struct phy_device *phydev)
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ctrl1000 |= ADVERTISE_1000HALF | master;
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if (features & SUPPORTED_1000baseT_Full)
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ctrl1000 |= ADVERTISE_1000FULL | master;
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phydev->advertising = phydev->supported = features;
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phydev->advertising = features;
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phydev->supported = features;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
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genphy_config_aneg(phydev);
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genphy_restart_aneg(phydev);
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@ -479,14 +480,14 @@ static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
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{
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return ksz9031_phy_extended_read(phydev, devaddr, regnum,
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MII_KSZ9031_MOD_DATA_NO_POST_INC);
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};
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}
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static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
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int devaddr, int regnum, u16 val)
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{
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return ksz9031_phy_extended_write(phydev, devaddr, regnum,
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MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
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};
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}
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static int ksz9031_config(struct phy_device *phydev)
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{
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@ -537,7 +538,7 @@ static struct phy_driver ksz886x_driver = {
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.shutdown = &genphy_shutdown,
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};
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int phy_micrel_init(void)
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int phy_micrel_ksz8xxx_init(void)
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{
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phy_register(&KSZ804_driver);
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phy_register(&KSZ8031_driver);
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364
drivers/net/phy/micrel_ksz90x1.c
Normal file
364
drivers/net/phy/micrel_ksz90x1.c
Normal file
@ -0,0 +1,364 @@
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/*
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* Micrel PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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* (C) 2012 NetModule AG, David Andrey, added KSZ9031
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* (C) Copyright 2017 Adaptrum, Inc.
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* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <micrel.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* KSZ9021 - KSZ9031 common
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*/
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#define MII_KSZ90xx_PHY_CTL 0x1f
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#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
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#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
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#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
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#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
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/* KSZ9021 PHY Registers */
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#define MII_KSZ9021_EXTENDED_CTRL 0x0b
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#define MII_KSZ9021_EXTENDED_DATAW 0x0c
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#define MII_KSZ9021_EXTENDED_DATAR 0x0d
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#define CTRL1000_PREFER_MASTER (1 << 10)
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#define CTRL1000_CONFIG_MASTER (1 << 11)
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#define CTRL1000_MANUAL_CONFIG (1 << 12)
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/* KSZ9031 PHY Registers */
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#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
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#define MII_KSZ9031_MMD_REG_DATA 0x0e
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static int ksz90xx_startup(struct phy_device *phydev)
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{
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unsigned phy_ctl;
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
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if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
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phydev->speed = SPEED_1000;
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else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
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phydev->speed = SPEED_100;
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else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
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phydev->speed = SPEED_10;
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return 0;
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}
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/* Common OF config bits for KSZ9021 and KSZ9031 */
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#ifdef CONFIG_DM_ETH
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struct ksz90x1_reg_field {
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const char *name;
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const u8 size; /* Size of the bitfield, in bits */
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const u8 off; /* Offset from bit 0 */
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const u8 dflt; /* Default value */
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};
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struct ksz90x1_ofcfg {
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const u16 reg;
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const u16 devad;
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const struct ksz90x1_reg_field *grp;
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const u16 grpsz;
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};
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static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
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{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
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{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
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};
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static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
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{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
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{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
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};
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static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
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{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
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{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
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};
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static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
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{ "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
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};
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static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
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{ "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
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};
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static int ksz90x1_of_config_group(struct phy_device *phydev,
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struct ksz90x1_ofcfg *ofcfg)
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{
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struct udevice *dev = phydev->dev;
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struct phy_driver *drv = phydev->drv;
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const int ps_to_regval = 60;
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int val[4];
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int i, changed = 0, offset, max;
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u16 regval = 0;
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if (!drv || !drv->writeext)
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return -EOPNOTSUPP;
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for (i = 0; i < ofcfg->grpsz; i++) {
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val[i] = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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ofcfg->grp[i].name, -1);
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offset = ofcfg->grp[i].off;
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if (val[i] == -1) {
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/* Default register value for KSZ9021 */
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regval |= ofcfg->grp[i].dflt << offset;
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} else {
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changed = 1; /* Value was changed in OF */
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/* Calculate the register value and fix corner cases */
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if (val[i] > ps_to_regval * 0xf) {
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max = (1 << ofcfg->grp[i].size) - 1;
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regval |= max << offset;
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} else {
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regval |= (val[i] / ps_to_regval) << offset;
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}
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}
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}
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if (!changed)
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return 0;
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return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
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}
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static int ksz9021_of_config(struct phy_device *phydev)
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{
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struct ksz90x1_ofcfg ofcfg[] = {
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{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
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{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
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{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
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};
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
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ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
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if (ret)
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return ret;
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}
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return 0;
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}
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static int ksz9031_of_config(struct phy_device *phydev)
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{
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struct ksz90x1_ofcfg ofcfg[] = {
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{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
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{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
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{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
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{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
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};
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
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ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
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if (ret)
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return ret;
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}
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return 0;
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}
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static int ksz9031_center_flp_timing(struct phy_device *phydev)
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{
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struct phy_driver *drv = phydev->drv;
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int ret = 0;
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if (!drv || !drv->writeext)
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return -EOPNOTSUPP;
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ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
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if (ret)
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return ret;
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ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
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return ret;
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}
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#else /* !CONFIG_DM_ETH */
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static int ksz9021_of_config(struct phy_device *phydev)
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{
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return 0;
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}
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static int ksz9031_of_config(struct phy_device *phydev)
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{
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return 0;
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}
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static int ksz9031_center_flp_timing(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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/*
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* KSZ9021
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*/
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int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
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{
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/* extended registers */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
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return phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9021_EXTENDED_DATAW, val);
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}
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int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
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{
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/* extended registers */
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phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
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return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
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}
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static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
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int regnum)
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{
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return ksz9021_phy_extended_read(phydev, regnum);
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}
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static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
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int devaddr, int regnum, u16 val)
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{
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return ksz9021_phy_extended_write(phydev, regnum, val);
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}
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static int ksz9021_config(struct phy_device *phydev)
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{
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unsigned ctrl1000 = 0;
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const unsigned master = CTRL1000_PREFER_MASTER |
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CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
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unsigned features = phydev->drv->features;
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int ret;
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ret = ksz9021_of_config(phydev);
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if (ret)
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return ret;
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if (getenv("disable_giga"))
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features &= ~(SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full);
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/* force master mode for 1000BaseT due to chip errata */
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if (features & SUPPORTED_1000baseT_Half)
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ctrl1000 |= ADVERTISE_1000HALF | master;
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if (features & SUPPORTED_1000baseT_Full)
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ctrl1000 |= ADVERTISE_1000FULL | master;
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phydev->advertising = features;
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phydev->supported = features;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
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genphy_config_aneg(phydev);
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genphy_restart_aneg(phydev);
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return 0;
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}
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static struct phy_driver ksz9021_driver = {
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.name = "Micrel ksz9021",
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.uid = 0x221610,
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.mask = 0xfffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &ksz9021_config,
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.startup = &ksz90xx_startup,
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.shutdown = &genphy_shutdown,
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.writeext = &ksz9021_phy_extwrite,
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.readext = &ksz9021_phy_extread,
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};
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/*
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* KSZ9031
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*/
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int ksz9031_phy_extended_write(struct phy_device *phydev,
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int devaddr, int regnum, u16 mode, u16 val)
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{
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/*select register addr for mmd*/
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
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/*select register for mmd*/
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_REG_DATA, regnum);
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/*setup mode*/
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phy_write(phydev, MDIO_DEVAD_NONE,
|
||||
MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
|
||||
/*write the value*/
|
||||
return phy_write(phydev, MDIO_DEVAD_NONE,
|
||||
MII_KSZ9031_MMD_REG_DATA, val);
|
||||
}
|
||||
|
||||
int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
|
||||
int regnum, u16 mode)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE,
|
||||
MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE,
|
||||
MII_KSZ9031_MMD_REG_DATA, regnum);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE,
|
||||
MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
|
||||
return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
|
||||
}
|
||||
|
||||
static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
|
||||
int regnum)
|
||||
{
|
||||
return ksz9031_phy_extended_read(phydev, devaddr, regnum,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC);
|
||||
}
|
||||
|
||||
static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
|
||||
int devaddr, int regnum, u16 val)
|
||||
{
|
||||
return ksz9031_phy_extended_write(phydev, devaddr, regnum,
|
||||
MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
|
||||
}
|
||||
|
||||
static int ksz9031_config(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
ret = ksz9031_of_config(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = ksz9031_center_flp_timing(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
return genphy_config(phydev);
|
||||
}
|
||||
|
||||
static struct phy_driver ksz9031_driver = {
|
||||
.name = "Micrel ksz9031",
|
||||
.uid = 0x221620,
|
||||
.mask = 0xfffff0,
|
||||
.features = PHY_GBIT_FEATURES,
|
||||
.config = &ksz9031_config,
|
||||
.startup = &ksz90xx_startup,
|
||||
.shutdown = &genphy_shutdown,
|
||||
.writeext = &ksz9031_phy_extwrite,
|
||||
.readext = &ksz9031_phy_extread,
|
||||
};
|
||||
|
||||
int phy_micrel_ksz90x1_init(void)
|
||||
{
|
||||
phy_register(&ksz9021_driver);
|
||||
phy_register(&ksz9031_driver);
|
||||
return 0;
|
||||
}
|
||||
@ -488,8 +488,11 @@ int phy_init(void)
|
||||
#ifdef CONFIG_PHY_MARVELL
|
||||
phy_marvell_init();
|
||||
#endif
|
||||
#ifdef CONFIG_PHY_MICREL
|
||||
phy_micrel_init();
|
||||
#ifdef CONFIG_PHY_MICREL_KSZ8XXX
|
||||
phy_micrel_ksz8xxx_init();
|
||||
#endif
|
||||
#ifdef CONFIG_PHY_MICREL_KSZ90X1
|
||||
phy_micrel_ksz90x1_init();
|
||||
#endif
|
||||
#ifdef CONFIG_PHY_NATSEMI
|
||||
phy_natsemi_init();
|
||||
|
||||
@ -266,7 +266,8 @@ int phy_davicom_init(void);
|
||||
int phy_et1011c_init(void);
|
||||
int phy_lxt_init(void);
|
||||
int phy_marvell_init(void);
|
||||
int phy_micrel_init(void);
|
||||
int phy_micrel_ksz8xxx_init(void);
|
||||
int phy_micrel_ksz90x1_init(void);
|
||||
int phy_natsemi_init(void);
|
||||
int phy_realtek_init(void);
|
||||
int phy_smsc_init(void);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user