arm: dts: aspeed: Update SPI flash node settings
For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.
AST2500:
- FMC:
CS number: 3
controller reg: 0x1e620000 - 0x1e62ffff
decoded address: 0x20000000 - 0x2fffffff
- SPI1:
CS number: 2
controller reg: 0x1e630000 - 0x1e630fff
decoded address: 0x30000000 - 0x37ffffff
- SPI2:
CS number: 2
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x38000000 - 0x3fffffff
AST2600:
- FMC:
CS number: 3
controller reg: 0x1e620000 - 0x1e62ffff
decoded address: 0x20000000 - 0x2fffffff
- SPI1:
CS number: 2
controller reg: 0x1e630000 - 0x1e630fff
decoded address: 0x30000000 - 0x3fffffff
- SPI2:
CS number: 3
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x50000000 - 0x5fffffff
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
This commit is contained in:
Chin-Ting Kuo
Tom Rini
parent
5150e908f5
commit
d37b4f37ea
@ -78,6 +78,39 @@
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pinctrl-0 = <&pinctrl_sd2_default>;
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};
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&fmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fwspics1_default>;
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flash@0 {
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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flash@1 {
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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&spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1cs1_default>;
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flash@0 {
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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&i2c3 {
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status = "okay";
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@ -57,23 +57,26 @@
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ranges;
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fmc: flash-controller@1e620000 {
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reg = < 0x1e620000 0xc4
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0x20000000 0x10000000 >;
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reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2500-fmc";
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clocks = <&scu ASPEED_CLK_AHB>;
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num-cs = <3>;
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status = "disabled";
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interrupts = <19>;
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@2 {
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reg = < 2 >;
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compatible = "jedec,spi-nor";
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@ -82,17 +85,20 @@
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};
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spi1: flash-controller@1e630000 {
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reg = < 0x1e630000 0xc4
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0x30000000 0x08000000 >;
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reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2500-spi";
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clocks = <&scu ASPEED_CLK_AHB>;
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num-cs = <2>;
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status = "disabled";
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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@ -101,17 +107,20 @@
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};
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spi2: flash-controller@1e631000 {
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reg = < 0x1e631000 0xc4
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0x38000000 0x08000000 >;
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reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2500-spi";
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clocks = <&scu ASPEED_CLK_AHB>;
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num-cs = <2>;
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status = "disabled";
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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@ -72,12 +72,10 @@
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&fmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fmcquad_default>;
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flash@0 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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@ -85,7 +83,6 @@
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};
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flash@1 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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@ -93,7 +90,6 @@
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};
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flash@2 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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@ -103,14 +99,12 @@
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&spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
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&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
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&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
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flash@0 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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@ -120,13 +114,11 @@
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&spi2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
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&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
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flash@0 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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@ -129,74 +129,78 @@
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};
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fmc: flash-controller@1e620000 {
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reg = < 0x1e620000 0xc4
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0x20000000 0x10000000 >;
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reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2600-fmc";
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status = "disabled";
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scu ASPEED_CLK_AHB>;
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num-cs = <3>;
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flash@0 {
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reg = < 0 >;
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reg = <0>;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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reg = <1>;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@2 {
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reg = < 2 >;
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reg = <2>;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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};
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spi1: flash-controller@1e630000 {
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reg = < 0x1e630000 0xc4
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0x30000000 0x08000000 >;
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reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2600-spi";
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clocks = <&scu ASPEED_CLK_AHB>;
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num-cs = <2>;
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status = "disabled";
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flash@0 {
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reg = < 0 >;
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reg = <0>;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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reg = <1>;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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};
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spi2: flash-controller@1e631000 {
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reg = < 0x1e631000 0xc4
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0x50000000 0x08000000 >;
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reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2600-spi";
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clocks = <&scu ASPEED_CLK_AHB>;
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num-cs = <3>;
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status = "disabled";
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flash@0 {
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reg = < 0 >;
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reg = <0>;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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reg = <1>;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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flash@2 {
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reg = < 2 >;
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reg = <2>;
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compatible = "jedec,spi-nor";
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status = "disabled";
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};
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