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dm: gpio: vf610: Add GPIO driver support

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Add GPIO driver support to Freescale VF610

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
This commit is contained in:
Bhuvanchandra DV
2015-06-01 18:37:16 +05:30
committed by Stefano Babic
parent ae89bb0d36
commit d348a943e7
7 changed files with 243 additions and 0 deletions
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26
arch/arm/imx-common/iomux-v3.c
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@@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit,
reg |= (value << start_bit);
writel(reg, base + group * 4);
}
#ifdef CONFIG_IOMUX_SHARE_CONF_REG
void imx_iomux_gpio_set_direction(unsigned int gpio,
unsigned int direction)
{
u32 reg;
/*
* Only on Vybrid the input/output buffer enable flags
* are part of the shared mux/conf register.
*/
reg = readl(base + (gpio << 2));
if (direction)
reg |= 0x2;
else
reg &= ~0x2;
writel(reg, base + (gpio << 2));
}
void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
{
*gpio_state = readl(base + (gpio << 2)) &
((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
}
#endif

29
arch/arm/include/asm/arch-vf610/gpio.h Normal file
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@@ -0,0 +1,29 @@
/*
* Copyright (C) 2015
* Bhuvanchandra DV, Toradex, Inc.
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_VF610_GPIO_H
#define __ASM_ARCH_VF610_GPIO_H
#define VYBRID_GPIO_COUNT 32
#define VF610_GPIO_DIRECTION_IN 0x0
#define VF610_GPIO_DIRECTION_OUT 0x1
/* GPIO registers */
struct vybrid_gpio_regs {
u32 gpio_pdor;
u32 gpio_psor;
u32 gpio_pcor;
u32 gpio_ptor;
u32 gpio_pdir;
};
struct vybrid_gpio_platdata {
unsigned int chip;
u32 base;
const char *port_name;
};
#endif /* __ASM_ARCH_VF610_GPIO_H */

5
arch/arm/include/asm/arch-vf610/imx-regs.h
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@@ -81,6 +81,11 @@
#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000)
#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040)
#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080)
#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0)
#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100)
/* AIPS 1 */
#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)

6
arch/arm/include/asm/imx-common/iomux-v3.h
View File

@@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
*/
void imx_iomux_set_gpr_register(int group, int start_bit,
int num_bits, int value);
#ifdef CONFIG_IOMUX_SHARE_CONF_REG
void imx_iomux_gpio_set_direction(unsigned int gpio,
unsigned int direction);
void imx_iomux_gpio_get_function(unsigned int gpio,
u32 *gpio_state);
#endif
/* macros for declaring and using pinmux array */
#if defined(CONFIG_MX6QDL)