Add command for handling DDR ECC registers on MPC8349EE MDS board.
This commit is contained in:
Marian Balakowicz
parent
97f98001a3
commit
d326f4a242
@ -2,6 +2,8 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Add command for handling DDR ECC registers on MPC8349EE MDS board.
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* Fix DDR ECC bit definitions for MPC83xx.
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* Add initial support for MPC8349E MDS board.
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@ -29,6 +29,7 @@
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <command.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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@ -277,3 +278,329 @@ void sdram_init(void)
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put("SDRAM on Local Bus is NOT available!\n");
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}
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#endif
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
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/*
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* ECC user commands
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*/
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void ecc_print_status(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile ddr8349_t *ddr = &immap->ddr;
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printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
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/* Interrupts */
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printf("Memory Error Interrupt Enable:\n");
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printf(" Multiple-Bit Error Interrupt Enable: %d\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
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printf(" Single-Bit Error Interrupt Enable: %d\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
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printf(" Memory Select Error Interrupt Enable: %d\n\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
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/* Error disable */
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printf("Memory Error Disable:\n");
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printf(" Multiple-Bit Error Disable: %d\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
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printf(" Sinle-Bit Error Disable: %d\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
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printf(" Memory Select Error Disable: %d\n\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
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/* Error injection */
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printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
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ddr->data_err_inject_hi, ddr->data_err_inject_lo);
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printf("Memory Data Path Error Injection Mask ECC:\n");
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printf(" ECC Mirror Byte: %d\n",
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(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
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printf(" ECC Injection Enable: %d\n",
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(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
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printf(" ECC Error Injection Mask: 0x%02x\n\n",
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ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
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/* SBE counter/threshold */
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printf("Memory Single-Bit Error Management (0..255):\n");
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printf(" Single-Bit Error Threshold: %d\n",
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(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
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printf(" Single-Bit Error Counter: %d\n\n",
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(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
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/* Error detect */
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printf("Memory Error Detect:\n");
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printf(" Multiple Memory Errors: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
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printf(" Multiple-Bit Error: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
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printf(" Single-Bit Error: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
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printf(" Memory Select Error: %d\n\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
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/* Capture data */
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printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
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printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
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ddr->capture_data_hi, ddr->capture_data_lo);
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printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
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ddr->capture_ecc & CAPTURE_ECC_ECE);
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printf("Memory Error Attributes Capture:\n");
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printf(" Data Beat Number: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
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printf(" Transaction Size: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
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printf(" Transaction Source: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
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printf(" Transaction Type: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
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printf(" Error Information Valid: %d\n\n",
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ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
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}
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int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile ddr8349_t *ddr = &immap->ddr;
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volatile u32 val;
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u64 *addr, count, val64;
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register u64 *i;
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if (argc > 4) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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if (argc == 2) {
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if (strcmp(argv[1], "status") == 0) {
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ecc_print_status();
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return 0;
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} else if (strcmp(argv[1], "captureclear") == 0) {
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ddr->capture_address = 0;
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ddr->capture_data_hi = 0;
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ddr->capture_data_lo = 0;
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ddr->capture_ecc = 0;
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ddr->capture_attributes = 0;
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return 0;
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}
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}
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if (argc == 3) {
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if (strcmp(argv[1], "sbecnt") == 0) {
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val = simple_strtoul(argv[2], NULL, 10);
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if (val > 255) {
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printf("Incorrect Counter value, should be 0..255\n");
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return 1;
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}
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val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
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val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
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ddr->err_sbe = val;
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return 0;
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} else if (strcmp(argv[1], "sbethr") == 0) {
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val = simple_strtoul(argv[2], NULL, 10);
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if (val > 255) {
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printf("Incorrect Counter value, should be 0..255\n");
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return 1;
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}
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val = (val << ECC_ERROR_MAN_SBET_SHIFT);
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val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
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ddr->err_sbe = val;
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return 0;
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} else if (strcmp(argv[1], "errdisable") == 0) {
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val = ddr->err_disable;
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if (strcmp(argv[2], "+sbe") == 0) {
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val |= ECC_ERROR_DISABLE_SBED;
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} else if (strcmp(argv[2], "+mbe") == 0) {
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val |= ECC_ERROR_DISABLE_MBED;
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} else if (strcmp(argv[2], "+mse") == 0) {
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val |= ECC_ERROR_DISABLE_MSED;
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} else if (strcmp(argv[2], "+all") == 0) {
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val |= (ECC_ERROR_DISABLE_SBED |
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ECC_ERROR_DISABLE_MBED |
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ECC_ERROR_DISABLE_MSED);
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} else if (strcmp(argv[2], "-sbe") == 0) {
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val &= ~ECC_ERROR_DISABLE_SBED;
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} else if (strcmp(argv[2], "-mbe") == 0) {
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val &= ~ECC_ERROR_DISABLE_MBED;
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} else if (strcmp(argv[2], "-mse") == 0) {
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val &= ~ECC_ERROR_DISABLE_MSED;
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} else if (strcmp(argv[2], "-all") == 0) {
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val &= ~(ECC_ERROR_DISABLE_SBED |
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ECC_ERROR_DISABLE_MBED |
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ECC_ERROR_DISABLE_MSED);
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} else {
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printf("Incorrect err_disable field\n");
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return 1;
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}
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ddr->err_disable = val;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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return 0;
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} else if (strcmp(argv[1], "errdetectclr") == 0) {
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val = ddr->err_detect;
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if (strcmp(argv[2], "mme") == 0) {
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val |= ECC_ERROR_DETECT_MME;
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} else if (strcmp(argv[2], "sbe") == 0) {
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val |= ECC_ERROR_DETECT_SBE;
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} else if (strcmp(argv[2], "mbe") == 0) {
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val |= ECC_ERROR_DETECT_MBE;
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} else if (strcmp(argv[2], "mse") == 0) {
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val |= ECC_ERROR_DETECT_MSE;
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} else if (strcmp(argv[2], "all") == 0) {
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val |= (ECC_ERROR_DETECT_MME |
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ECC_ERROR_DETECT_MBE |
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ECC_ERROR_DETECT_SBE |
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ECC_ERROR_DETECT_MSE);
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} else {
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printf("Incorrect err_detect field\n");
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return 1;
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}
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ddr->err_detect = val;
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return 0;
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} else if (strcmp(argv[1], "injectdatahi") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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ddr->data_err_inject_hi = val;
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return 0;
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} else if (strcmp(argv[1], "injectdatalo") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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ddr->data_err_inject_lo = val;
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return 0;
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} else if (strcmp(argv[1], "injectecc") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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if (val > 0xff) {
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printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
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return 1;
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}
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val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
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ddr->ecc_err_inject = val;
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return 0;
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} else if (strcmp(argv[1], "inject") == 0) {
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val = ddr->ecc_err_inject;
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if (strcmp(argv[2], "en") == 0)
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val |= ECC_ERR_INJECT_EIEN;
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else if (strcmp(argv[2], "dis") == 0)
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val &= ~ECC_ERR_INJECT_EIEN;
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else
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printf("Incorrect command\n");
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ddr->ecc_err_inject = val;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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return 0;
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} else if (strcmp(argv[1], "mirror") == 0) {
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val = ddr->ecc_err_inject;
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if (strcmp(argv[2], "en") == 0)
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val |= ECC_ERR_INJECT_EMB;
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else if (strcmp(argv[2], "dis") == 0)
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val &= ~ECC_ERR_INJECT_EMB;
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else
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printf("Incorrect command\n");
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ddr->ecc_err_inject = val;
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return 0;
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}
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}
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if (argc == 4) {
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if (strcmp(argv[1], "test") == 0) {
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addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
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count = simple_strtoul(argv[3], NULL, 16);
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if ((u32)addr % 8) {
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printf("Address not alligned on double word boundary\n");
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return 1;
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}
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disable_interrupts();
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icache_disable();
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for (i = addr; i < addr + count; i++) {
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/* enable injects */
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ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* write memory location injecting errors */
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*i = 0x1122334455667788ULL;
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__asm__ __volatile__ ("sync");
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/* disable injects */
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ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* read data, this generates ECC error */
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val64 = *i;
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__asm__ __volatile__ ("sync");
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/* disable errors for ECC */
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ddr->err_disable |= ~ECC_ERROR_ENABLE;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* re-initialize memory, write the location again
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* NOT injecting errors this time */
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*i = 0xcafecafecafecafeULL;
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__asm__ __volatile__ ("sync");
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/* enable errors for ECC */
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ddr->err_disable &= ECC_ERROR_ENABLE;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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}
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icache_enable();
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enable_interrupts();
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return 0;
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}
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}
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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U_BOOT_CMD(
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ecc, 4, 0, do_ecc,
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"ecc - support for DDR ECC features\n",
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"status - print out status info\n"
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"ecc captureclear - clear capture regs data\n"
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"ecc sbecnt <val> - set Single-Bit Error counter\n"
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"ecc sbethr <val> - set Single-Bit Threshold\n"
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"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
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" [-|+]sbe - Single-Bit Error\n"
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" [-|+]mbe - Multiple-Bit Error\n"
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" [-|+]mse - Memory Select Error\n"
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" [-|+]all - all errors\n"
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"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
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" mme - Multiple Memory Errors\n"
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" sbe - Single-Bit Error\n"
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" mbe - Multiple-Bit Error\n"
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" mse - Memory Select Error\n"
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" all - all errors\n"
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"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
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"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
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"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
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"ecc inject <en|dis> - enable/disable error injection\n"
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"ecc mirror <en|dis> - enable/disable mirror byte\n"
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"ecc test <addr> <cnt> - test mem region:\n"
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" - enables injects\n"
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" - writes pattern injecting errors\n"
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" - disables injects\n"
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" - reads pattern back, generates error\n"
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" - re-inits memory"
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);
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#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
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135
doc/README.mpc8349emds.ddrecc
Normal file
135
doc/README.mpc8349emds.ddrecc
Normal file
@ -0,0 +1,135 @@
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Use cases for DDR 'ecc' command:
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================================
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Before executing particular tests reset target board or clear status registers:
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=> ecc captureclear
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=> ecc errdetectclr all
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=> ecc sbecnt 0
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Injecting Single-Bit Errors
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---------------------------
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1. Set 1 bit in Data Path Error Inject Mask
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=> ecc injectdatahi 1
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2. Run test over some memory region
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=> ecc test 200000 10
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3. Check ECC status
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=> ecc status
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...
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Memory Data Path Error Injection Mask High/Low: 00000001 00000000
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...
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Memory Single-Bit Error Management (0..255):
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Single-Bit Error Threshold: 255
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Single Bit Error Counter: 16
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...
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Memory Error Detect:
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Multiple Memory Errors: 0
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Multiple-Bit Error: 0
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Single-Bit Error: 0
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...
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16 errors were generated, Single-Bit Error flag was not set as Single Bit Error
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Counter did not reach Single-Bit Error Threshold.
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4. Make sure used memory region got re-initialized with 0xcafecafe pattern
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=> md 200000
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00200000: cafecafe cafecafe cafecafe cafecafe ................
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00200010: cafecafe cafecafe cafecafe cafecafe ................
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00200020: cafecafe cafecafe cafecafe cafecafe ................
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00200030: cafecafe cafecafe cafecafe cafecafe ................
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00200040: cafecafe cafecafe cafecafe cafecafe ................
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00200050: cafecafe cafecafe cafecafe cafecafe ................
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00200060: cafecafe cafecafe cafecafe cafecafe ................
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00200070: cafecafe cafecafe cafecafe cafecafe ................
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00200080: deadbeef deadbeef deadbeef deadbeef ................
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00200090: deadbeef deadbeef deadbeef deadbeef ................
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Injecting Multiple-Bit Errors
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-----------------------------
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1. Set more than 1 bit in Data Path Error Inject Mask
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=> ecc injectdatahi 5
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2. Run test over some memory region
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=> ecc test 200000 10
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3. Check ECC status
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=> ecc status
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...
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Memory Data Path Error Injection Mask High/Low: 00000005 00000000
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...
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Memory Error Detect:
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Multiple Memory Errors: 1
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Multiple-Bit Error: 1
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Single-Bit Error: 0
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...
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Observe that both Multiple Memory Errors and Multiple-Bit Error flags are set.
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4. Make sure used memory region got re-initialized with 0xcafecafe pattern
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=> md 200000
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00200000: cafecafe cafecafe cafecafe cafecafe ................
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00200010: cafecafe cafecafe cafecafe cafecafe ................
|
||||
00200020: cafecafe cafecafe cafecafe cafecafe ................
|
||||
00200030: cafecafe cafecafe cafecafe cafecafe ................
|
||||
00200040: cafecafe cafecafe cafecafe cafecafe ................
|
||||
00200050: cafecafe cafecafe cafecafe cafecafe ................
|
||||
00200060: cafecafe cafecafe cafecafe cafecafe ................
|
||||
00200070: cafecafe cafecafe cafecafe cafecafe ................
|
||||
00200080: deadbeef deadbeef deadbeef deadbeef ................
|
||||
00200090: deadbeef deadbeef deadbeef deadbeef ................
|
||||
|
||||
|
||||
Test Single-Bit Error Counter and Threshold
|
||||
-------------------------------------------
|
||||
|
||||
1. Set 1 bit in Data Path Error Inject Mask
|
||||
|
||||
=> ecc injectdatahi 1
|
||||
|
||||
2. Enable error injection
|
||||
|
||||
=> ecc inject en
|
||||
|
||||
3. Let u-boot run for a with Single-Bit error injection enabled
|
||||
|
||||
4. Disable error injection
|
||||
|
||||
=> ecc inject dis
|
||||
|
||||
4. Check status
|
||||
|
||||
=> ecc status
|
||||
|
||||
...
|
||||
Memory Single-Bit Error Management (0..255):
|
||||
Single-Bit Error Threshold: 255
|
||||
Single Bit Error Counter: 60
|
||||
|
||||
Memory Error Detect:
|
||||
Multiple Memory Errors: 1
|
||||
Multiple-Bit Error: 0
|
||||
Single-Bit Error: 1
|
||||
...
|
||||
|
||||
Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter
|
||||
reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that
|
||||
is Counter reached Threshold more than one time (it wraps back after reaching
|
||||
Threshold).
|
||||
|
||||
|
||||
@ -70,6 +70,7 @@
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
|
||||
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
|
||||
|
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user