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fsl_ddr: Move DDR config options to driver Kconfig

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Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
York Sun
2016-12-28 08:43:40 -08:00
committed by Tom Rini
parent a105503851
commit d26e34c4c4
138 changed files with 262 additions and 237 deletions
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47
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@@ -3,8 +3,10 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_DDR_BE if SYS_FSL_DDR
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
@@ -49,47 +51,6 @@ config SYS_FSL_SRDS_2
config SYS_HAS_SERDES
bool
config SYS_FSL_DDR
bool "Freescale DDR driver"
help
Select Freescale General DDR driver, shared between most Freescale
PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
based Layerscape SoCs (such as ls2080a).
config SYS_FSL_DDR_BE
bool
default y
help
Access DDR registers in big-endian.
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50
config SYS_FSL_DDR_VER_50
bool
config SYS_FSL_DDRC_ARM_GEN3
bool
config SYS_FSL_DDRC_GEN4
bool
config SYS_FSL_DDR3
bool "Freescale DDR3 controller"
depends on !SYS_FSL_DDR4
select SYS_FSL_DDR
select SYS_FSL_DDRC_ARM_GEN3
help
Enable Freescale DDR3 controller on ARM-based SoCs.
config SYS_FSL_DDR4
bool "Freescale DDR4 controller"
select SYS_FSL_DDR
select SYS_FSL_DDRC_GEN4
help
Enable Freescale DDR4 controller.
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1021A

57
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@@ -8,28 +8,33 @@ config ARCH_LS1012A
config ARCH_LS1043A
bool
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
config ARCH_LS1046A
bool
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_DDR4
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
config ARCH_LS2080A
bool
select FSL_LSCH3
select SYS_FSL_DDR4
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_2
@@ -71,9 +76,6 @@ config FSL_PPA_ARMV8_PSCI
implemented under the common ARMv8 PSCI framework.
endmenu
config SYS_FSL_MMDC
bool
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
@@ -129,49 +131,4 @@ config SYS_FSL_SRDS_2
config SYS_HAS_SERDES
bool
config SYS_FSL_DDR
bool "Freescale DDR driver"
help
Select Freescale General DDR driver, shared between most Freescale
PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
based Layerscape SoCs (such as ls2080a).
config SYS_FSL_DDR_BE
bool
help
Access DDR registers in big-endian.
config SYS_FSL_DDR_LE
bool
help
Access DDR registers in little-endian.
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50
config SYS_FSL_DDR_VER_50
bool
config SYS_FSL_DDRC_ARM_GEN3
bool
config SYS_FSL_DDRC_GEN4
bool
config SYS_FSL_DDR3
bool "Freescale DDR3 controller"
depends on !SYS_FSL_DDR4
select SYS_FSL_DDR
select SYS_FSL_DDRC_ARM_GEN3
help
Enable Freescale DDR3 controller on ARM-based SoCs.
config SYS_FSL_DDR4
bool "Freescale DDR4 controller"
select SYS_FSL_DDR
select SYS_FSL_DDRC_GEN4
help
Enable Freescale DDR4 controller.
endmenu