clk: renesas: Split out code shared between Gen2 and Gen3
Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
65f1bbf678
commit
d26286715f
@ -1,3 +1,4 @@
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obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
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obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
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obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
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@ -21,6 +21,7 @@
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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#define CPG_RST_MODEMR 0x0060
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@ -33,47 +34,6 @@
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#define CPG_RPC_POSTDIV_MASK 0x7
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#define CPG_RPC_POSTDIV_OFFSET 0
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/*
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* Module Standby and Software Reset register offets.
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*
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* If the registers exist, these are valid for SH-Mobile, R-Mobile,
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* R-Car Gen2, R-Car Gen3, and RZ/G1.
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* These are NOT valid for R-Car Gen1 and RZ/A1!
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*/
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/*
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* Module Stop Status Register offsets
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*/
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static const u16 mstpsr[] = {
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0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
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0x9A0, 0x9A4, 0x9A8, 0x9AC,
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};
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#define MSTPSR(i) mstpsr[i]
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/*
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* System Module Stop Control Register offsets
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*/
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static const u16 smstpcr[] = {
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0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
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0x990, 0x994, 0x998, 0x99C,
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};
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#define SMSTPCR(i) smstpcr[i]
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/* Realtime Module Stop Control Register offsets */
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#define RMSTPCR(i) (smstpcr[i] - 0x20)
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/* Modem Module Stop Control Register offsets (r8a73a4) */
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#define MMSTPCR(i) (smstpcr[i] + 0x20)
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x940 + (i) * 4)
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/*
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* SDn Clock
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*/
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@ -126,99 +86,24 @@ static const struct sd_div_table cpg_sd_div_table[] = {
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
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};
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static bool gen3_clk_is_mod(struct clk *clk)
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{
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return (clk->id >> 16) == CPG_MOD;
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}
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static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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struct cpg_mssr_info *info = priv->info;
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const unsigned long clkid = clk->id & 0xffff;
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int i;
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if (!gen3_clk_is_mod(clk))
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return -EINVAL;
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for (i = 0; i < info->mod_clk_size; i++) {
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if (info->mod_clk[i].id !=
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(info->mod_clk_base + MOD_CLK_PACK(clkid)))
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continue;
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*mssr = &info->mod_clk[i];
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return 0;
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}
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return -ENODEV;
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}
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static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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struct cpg_mssr_info *info = priv->info;
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const unsigned long clkid = clk->id & 0xffff;
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int i;
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if (gen3_clk_is_mod(clk))
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return -EINVAL;
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for (i = 0; i < info->core_clk_size; i++) {
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if (info->core_clk[i].id != clkid)
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continue;
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*core = &info->core_clk[i];
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return 0;
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}
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return -ENODEV;
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}
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static int gen3_clk_get_parent(struct clk *clk, struct clk *parent)
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{
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const struct cpg_core_clk *core;
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const struct mssr_mod_clk *mssr;
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int ret;
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if (gen3_clk_is_mod(clk)) {
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ret = gen3_clk_get_mod(clk, &mssr);
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if (ret)
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return ret;
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parent->id = mssr->parent;
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} else {
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ret = gen3_clk_get_core(clk, &core);
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if (ret)
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return ret;
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if (core->type == CLK_TYPE_IN)
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parent->id = ~0; /* Top-level clock */
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else
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parent->id = core->parent;
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}
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parent->dev = clk->dev;
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return 0;
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}
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static int gen3_clk_setup_sdif_div(struct clk *clk)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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struct cpg_mssr_info *info = priv->info;
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const struct cpg_core_clk *core;
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struct clk parent;
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int ret;
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ret = gen3_clk_get_parent(clk, &parent);
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ret = renesas_clk_get_parent(clk, info, &parent);
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if (ret) {
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printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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if (gen3_clk_is_mod(&parent))
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if (renesas_clk_is_mod(&parent))
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return 0;
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ret = gen3_clk_get_core(&parent, &core);
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ret = renesas_clk_get_core(&parent, info, &core);
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if (ret)
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return ret;
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@ -232,42 +117,22 @@ static int gen3_clk_setup_sdif_div(struct clk *clk)
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return 0;
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}
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static int gen3_clk_endisable(struct clk *clk, bool enable)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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const unsigned long clkid = clk->id & 0xffff;
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const unsigned int reg = clkid / 100;
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const unsigned int bit = clkid % 100;
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const u32 bitmask = BIT(bit);
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int ret;
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if (!gen3_clk_is_mod(clk))
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return -EINVAL;
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debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
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clkid, reg, bit, enable ? "ON" : "OFF");
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if (enable) {
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ret = gen3_clk_setup_sdif_div(clk);
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if (ret)
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return ret;
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clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
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return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
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bitmask, 0, 100, 0);
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} else {
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setbits_le32(priv->base + SMSTPCR(reg), bitmask);
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return 0;
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}
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}
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static int gen3_clk_enable(struct clk *clk)
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{
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return gen3_clk_endisable(clk, true);
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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int ret = gen3_clk_setup_sdif_div(clk);
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if (ret)
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return ret;
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return renesas_clk_endisable(clk, priv->base, true);
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}
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static int gen3_clk_disable(struct clk *clk)
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{
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return gen3_clk_endisable(clk, false);
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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return renesas_clk_endisable(clk, priv->base, false);
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}
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static ulong gen3_clk_get_rate(struct clk *clk)
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@ -283,20 +148,20 @@ static ulong gen3_clk_get_rate(struct clk *clk)
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debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
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ret = gen3_clk_get_parent(clk, &parent);
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ret = renesas_clk_get_parent(clk, info, &parent);
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if (ret) {
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printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
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return ret;
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}
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if (gen3_clk_is_mod(clk)) {
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if (renesas_clk_is_mod(clk)) {
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rate = gen3_clk_get_rate(&parent);
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debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
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__func__, __LINE__, parent.id, rate);
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return rate;
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}
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ret = gen3_clk_get_core(clk, &core);
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ret = renesas_clk_get_core(clk, info, &core);
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if (ret)
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return ret;
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@ -491,21 +356,6 @@ int gen3_clk_probe(struct udevice *dev)
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int gen3_clk_remove(struct udevice *dev)
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{
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struct gen3_clk_priv *priv = dev_get_priv(dev);
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struct cpg_mssr_info *info = priv->info;
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unsigned int i;
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/* Stop TMU0 */
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clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
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/* Stop module clock */
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for (i = 0; i < info->mstp_table_size; i++) {
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clrsetbits_le32(priv->base + SMSTPCR(i),
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info->mstp_table[i].sdis,
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info->mstp_table[i].sen);
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clrsetbits_le32(priv->base + RMSTPCR(i),
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info->mstp_table[i].rdis,
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info->mstp_table[i].ren);
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}
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return 0;
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return renesas_clk_remove(priv->base, priv->info);
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}
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175
drivers/clk/renesas/renesas-cpg-mssr.c
Normal file
175
drivers/clk/renesas/renesas-cpg-mssr.c
Normal file
@ -0,0 +1,175 @@
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/*
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* Renesas RCar Gen3 CPG MSSR driver
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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/*
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* Module Standby and Software Reset register offets.
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*
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* If the registers exist, these are valid for SH-Mobile, R-Mobile,
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* R-Car Gen2, R-Car Gen3, and RZ/G1.
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* These are NOT valid for R-Car Gen1 and RZ/A1!
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*/
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/*
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* Module Stop Status Register offsets
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*/
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static const u16 mstpsr[] = {
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0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
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0x9A0, 0x9A4, 0x9A8, 0x9AC,
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};
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#define MSTPSR(i) mstpsr[i]
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/*
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* System Module Stop Control Register offsets
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*/
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static const u16 smstpcr[] = {
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0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
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0x990, 0x994, 0x998, 0x99C,
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};
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#define SMSTPCR(i) smstpcr[i]
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/* Realtime Module Stop Control Register offsets */
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#define RMSTPCR(i) (smstpcr[i] - 0x20)
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/* Modem Module Stop Control Register offsets (r8a73a4) */
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#define MMSTPCR(i) (smstpcr[i] + 0x20)
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x940 + (i) * 4)
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bool renesas_clk_is_mod(struct clk *clk)
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{
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return (clk->id >> 16) == CPG_MOD;
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}
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int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
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const struct mssr_mod_clk **mssr)
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{
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const unsigned long clkid = clk->id & 0xffff;
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int i;
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for (i = 0; i < info->mod_clk_size; i++) {
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if (info->mod_clk[i].id !=
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(info->mod_clk_base + MOD_CLK_PACK(clkid)))
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continue;
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*mssr = &info->mod_clk[i];
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return 0;
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}
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return -ENODEV;
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}
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int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
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const struct cpg_core_clk **core)
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{
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const unsigned long clkid = clk->id & 0xffff;
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int i;
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for (i = 0; i < info->core_clk_size; i++) {
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if (info->core_clk[i].id != clkid)
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continue;
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*core = &info->core_clk[i];
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return 0;
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}
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return -ENODEV;
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}
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int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
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struct clk *parent)
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{
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const struct cpg_core_clk *core;
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const struct mssr_mod_clk *mssr;
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int ret;
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if (renesas_clk_is_mod(clk)) {
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ret = renesas_clk_get_mod(clk, info, &mssr);
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if (ret)
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return ret;
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parent->id = mssr->parent;
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} else {
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ret = renesas_clk_get_core(clk, info, &core);
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if (ret)
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return ret;
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if (core->type == CLK_TYPE_IN)
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parent->id = ~0; /* Top-level clock */
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else
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parent->id = core->parent;
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}
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parent->dev = clk->dev;
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return 0;
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}
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int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
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{
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const unsigned long clkid = clk->id & 0xffff;
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const unsigned int reg = clkid / 100;
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const unsigned int bit = clkid % 100;
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const u32 bitmask = BIT(bit);
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if (!renesas_clk_is_mod(clk))
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return -EINVAL;
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debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
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clkid, reg, bit, enable ? "ON" : "OFF");
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if (enable) {
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clrbits_le32(base + SMSTPCR(reg), bitmask);
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return wait_for_bit("MSTP", base + MSTPSR(reg),
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bitmask, 0, 100, 0);
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} else {
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setbits_le32(base + SMSTPCR(reg), bitmask);
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return 0;
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}
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}
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int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
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{
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unsigned int i;
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/* Stop TMU0 */
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clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
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/* Stop module clock */
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for (i = 0; i < info->mstp_table_size; i++) {
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clrsetbits_le32(base + SMSTPCR(i),
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info->mstp_table[i].sdis,
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info->mstp_table[i].sen);
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clrsetbits_le32(base + RMSTPCR(i),
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info->mstp_table[i].rdis,
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info->mstp_table[i].ren);
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}
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return 0;
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}
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@ -95,4 +95,14 @@ struct mstp_stop_table {
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#define TSTR0 0x04
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#define TSTR0_STR0 BIT(0)
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bool renesas_clk_is_mod(struct clk *clk);
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int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
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const struct mssr_mod_clk **mssr);
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int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
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const struct cpg_core_clk **core);
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int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
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struct clk *parent);
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int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
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int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
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#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
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