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Merge branch 'master' of http://www.denx.de/git/u-boot

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This commit is contained in:
Jon Loeliger
2006-10-19 12:03:44 -05:00
parent 4d45f69e36 fcfed4f2f2
commit d22200f020
16 changed files with 1125 additions and 13 deletions
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50
board/v38b/Makefile Normal file
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#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o ethaddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

32
board/v38b/config.mk Normal file
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#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# MarelV38B board
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
TEXT_BASE = 0xFF000000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

254
board/v38b/ethaddr.c Normal file
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/*
*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc5xxx.h>
#define GPIO_ENABLE (MPC5XXX_WU_GPIO)
/* Open Drain Emulation Register */
#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04)
/* Data Direction Register */
#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08)
/* Data Value Out Register */
#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C)
/* Interrupt Enable Register */
#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10)
/* Individual Interrupt Enable Register */
#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14)
/* Interrupt Type Register */
#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18)
/* Master Enable Register */
#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C)
/* Data Input Value Register */
#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20)
/* Status Register */
#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24)
#define PSC6_0 0x10000000
#define WKUP_7 0x80000000
/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */
#define GPIO_PIN PSC6_0
#define NO_ERROR 0
#define ERR_NO_NUMBER 1
#define ERR_BAD_NUMBER 2
typedef volatile unsigned long GPIO_REG;
typedef GPIO_REG *GPIO_REG_PTR;
static int is_high(void);
static int check_device(void);
static void io_out(int value);
static void io_input(void);
static void io_output(void);
static void init_gpio(void);
static void read_byte(unsigned char *data);
static void write_byte(unsigned char command);
void read_2501_memory(unsigned char *psernum, unsigned char *perr);
void board_get_enetaddr(uchar *enetaddr);
static int is_high()
{
return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN);
}
static void io_out(int value)
{
if (value)
*((vu_long *) GPIO_DVOR) |= GPIO_PIN;
else
*((vu_long *) GPIO_DVOR) &= ~GPIO_PIN;
}
static void io_input()
{
*((vu_long *) GPIO_DDR) &= ~GPIO_PIN;
udelay(3); /* allow input to settle */
}
static void io_output()
{
*((vu_long *) GPIO_DDR) |= GPIO_PIN;
}
static void init_gpio()
{
*((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */
}
void read_2501_memory(unsigned char *psernum, unsigned char *perr)
{
#define NBYTES 28
unsigned char crcval, i;
unsigned char buf[NBYTES];
*perr = 0;
crcval = 0;
for (i=0; i<NBYTES; i++)
if (!check_device())
*perr = ERR_NO_NUMBER;
else {
*perr = NO_ERROR;
write_byte(0xCC); /* skip ROM (0xCC) */
write_byte(0xF0); /* Read memory command 0xF0 */
write_byte(0x00); /* Address TA1=0, TA2=0 */
write_byte(0x00);
read_byte(&crcval); /* Read CRC of address and command */
for (i=0; i<NBYTES; i++)
read_byte( &buf[i] );
}
if (strncmp((const char*) &buf[11], "MAREL IEEE 802.3", 16)) {
*perr = ERR_BAD_NUMBER;
psernum[0] = 0x00;
psernum[1] = 0xE0;
psernum[2] = 0xEE;
psernum[3] = 0xFF;
psernum[4] = 0xFF;
psernum[5] = 0xFF;
}
else {
psernum[0] = 0x00;
psernum[1] = 0xE0;
psernum[2] = 0xEE;
psernum[3] = buf[7];
psernum[4] = buf[6];
psernum[5] = buf[5];
}
}
static int check_device()
{
int found;
io_output();
io_out(0);
udelay(500); /* must be at least 480 us low pulse */
io_input();
udelay(60);
found = (is_high() == 0) ? 1 : 0;
udelay(500); /* must be at least 480 us low pulse */
return found;
}
static void write_byte(unsigned char command)
{
char i;
for (i=0; i<8; i++) {
/* 1 us to 15 us low pulse starts bit slot */
/* Start with high pulse for 3 us */
io_input();
udelay(3);
io_out(0);
io_output();
udelay(3);
if (command & 0x01) {
/* 60 us high for 1-bit */
io_input();
udelay(60);
}
else {
/* 60 us low for 0-bit */
udelay(60);
}
/* Leave pin as input */
io_input();
command = command >> 1;
}
}
static void read_byte(unsigned char *data)
{
unsigned char i, rdat = 0;
for (i=0; i<8; i++) {
/* read one bit from one-wire device */
/* 1 - 15 us low starts bit slot */
io_out(0);
io_output();
udelay(0);
/* allow line to be pulled high */
io_input();
/* delay 10 us */
udelay(10);
/* now sample input status */
if (is_high())
rdat = (rdat >> 1) | 0x80;
else
rdat = rdat >> 1;
udelay(60); /* at least 60 us */
}
/* copy the return value */
*data = rdat;
}
void board_get_enetaddr(uchar *enetaddr)
{
unsigned char sn[6], err=NO_ERROR;
init_gpio();
read_2501_memory(sn, &err);
if (err == NO_ERROR) {
sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
printf("MAC address: %s\n", enetaddr);
setenv("ethaddr", enetaddr);
}
else {
sprintf(enetaddr, "00:01:02:03:04:05");
printf("Error reading MAC address.\n");
printf("Setting default to %s\n", enetaddr);
setenv("ethaddr", enetaddr);
}
}

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board/v38b/u-boot.lds Normal file
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/*
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc5xxx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

252
board/v38b/v38b.c Normal file
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/*
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc5xxx.h>
#include <asm/processor.h>
#ifndef CFG_RAMBOOT
static void sdram_start(int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif /* SDRAM_DDR */
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif /* !CFG_RAMBOOT */
long int initdram(int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
uint svr, pvr;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif /* SDRAM_DDR */
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else
dramsize = test2;
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20))
dramsize = 0;
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0)
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
else
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
/* let SDRAM CS1 start right after CS0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else
dramsize2 = test2;
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20))
dramsize2 = 0;
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0)
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
else
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
#else /* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13)
dramsize = (1 << (dramsize - 0x13)) << 20;
else
dramsize = 0;
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13)
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
else
dramsize2 = 0;
#endif /* CFG_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
__asm__ volatile ("sync");
}
return dramsize + dramsize2;
}
int checkboard (void)
{
puts("Board: MarelV38B\n");
return 0;
}
int board_early_init_r(void)
{
/*
* Now, when we are in RAM, enable flash write access for detection process.
* Note that CS_BOOT cannot be cleared when executing in flash.
*/
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
return 0;
}
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void init_ide_reset(void)
{
debug("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
/* Deassert reset */
*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
}
void ide_set_reset(int idereset)
{
debug("ide_reset(%d)\n", idereset);
if (idereset) {
*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
/* Make a delay. MPC5200 spec says 25 usec min */
udelay(500000);
} else
*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
void led_d4_on(void)
{
/* TIMER7 as GPIO output low */
*(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24;
}
void led_d4_off(void)
{
/* TIMER7 as GPIO output high */
*(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34;
}
void hw_watchdog_reset(void)
{
/* TODO fill this in */
}