misc: Add MPC83xx serdes driver
Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six
Simon Glass
parent
19fbdca47b
commit
d2166319df
@ -0,0 +1,24 @@
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MPC83xx SerDes controller devices
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MPC83xx SoCs contain a built-in SerDes controller that determines which
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protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines
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and how the lines are configured.
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Required properties:
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- compatible: must be "fsl,mpc83xx-serdes"
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- reg: must point to the serdes controller's register map
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- proto: selects for which protocol the serdes lines are configured. One of
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"sata", "pex", "pex-x2", "sgmii"
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- serdes-clk: determines the frequency the serdes lines are configured for. One
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of 100, 125, 150.
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- vdd: determines whether 1.0V core VDD is used or not
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Example:
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SERDES: serdes@e3000 {
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reg = <0xe3000 0x200>;
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compatible = "fsl,mpc83xx-serdes";
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proto = "pex";
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serdes-clk = <100>;
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vdd;
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};
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@ -529,6 +529,7 @@ F: include/dt-bindings/clk/mpc83xx-clk.h
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F: drivers/timer/mpc83xx_timer.c
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F: drivers/timer/mpc83xx_timer.c
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F: drivers/cpu/mpc83xx_cpu.c
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F: drivers/cpu/mpc83xx_cpu.c
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F: drivers/cpu/mpc83xx_cpu.h
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F: drivers/cpu/mpc83xx_cpu.h
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F: drivers/misc/mpc83xx_serdes.c
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F: arch/powerpc/cpu/mpc83xx/
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F: arch/powerpc/cpu/mpc83xx/
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F: arch/powerpc/include/asm/arch-mpc83xx/
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F: arch/powerpc/include/asm/arch-mpc83xx/
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@ -8,6 +8,8 @@
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* Author: Li Yang <leoli@freescale.com>
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* Author: Li Yang <leoli@freescale.com>
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*/
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*/
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#ifndef CONFIG_MPC83XX_SERDES
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#include <config.h>
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#include <config.h>
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#include <common.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/io.h>
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@ -148,3 +150,5 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
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tmp |= FSL_SRDSRSTCTL_RST;
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tmp |= FSL_SRDSRSTCTL_RST;
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out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
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out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
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}
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}
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#endif /* !CONFIG_MPC83XX_SERDES */
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@ -6,6 +6,8 @@
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#ifndef __FSL_MPC83XX_SERDES_H
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#ifndef __FSL_MPC83XX_SERDES_H
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#define __FSL_MPC83XX_SERDES_H
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#define __FSL_MPC83XX_SERDES_H
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#ifndef CONFIG_MPC83XX_SERDES
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#include <config.h>
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#include <config.h>
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#define FSL_SERDES_CLK_100 (0 << 28)
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#define FSL_SERDES_CLK_100 (0 << 28)
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@ -19,4 +21,6 @@
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extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
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extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
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#endif /* !CONFIG_MPC83XX_SERDES */
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#endif /* __FSL_MPC83XX_SERDES_H */
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#endif /* __FSL_MPC83XX_SERDES_H */
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@ -288,4 +288,11 @@ config GDSYS_IOEP
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depends on MISC
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depends on MISC
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help
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help
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Support gdsys FPGA's IO endpoint driver.
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Support gdsys FPGA's IO endpoint driver.
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config MPC83XX_SERDES
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bool "Enable MPC83xx serdes driver"
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depends on MISC
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help
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Support for serdes found on MPC83xx SoCs.
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endmenu
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endmenu
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@ -55,3 +55,4 @@ obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
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obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
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obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
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obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
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obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
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obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
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obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
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obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
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185
drivers/misc/mpc83xx_serdes.c
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185
drivers/misc/mpc83xx_serdes.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*
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* base on the MPC83xx serdes initialization, which is
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*
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* Copyright 2007,2011 Freescale Semiconductor, Inc.
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* Copyright (C) 2008 MontaVista Software, Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <mapmem.h>
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#include <misc.h>
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#include "mpc83xx_serdes.h"
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/**
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* struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
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* @regs: The device's register map
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* @rfcks: Variable to keep the serdes reference clock selection set during
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* initialization in (is or'd to every value written to SRDSCR4)
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*/
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struct mpc83xx_serdes_priv {
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struct mpc83xx_serdes_regs *regs;
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u32 rfcks;
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};
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/**
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* setup_sata() - Configure the SerDes device to SATA mode
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* @dev: The device to configure
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*/
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static void setup_sata(struct udevice *dev)
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{
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struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
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/* Set and clear reset bits */
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setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
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udelay(1000);
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clrbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
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/* Configure SRDSCR0 */
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clrsetbits_be32(&priv->regs->srdscr0,
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SRDSCR0_TXEQA_MASK | SRDSCR0_TXEQE_MASK,
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SRDSCR0_TXEQA_SATA | SRDSCR0_TXEQE_SATA);
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/* Configure SRDSCR1 */
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clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
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/* Configure SRDSCR2 */
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clrsetbits_be32(&priv->regs->srdscr2,
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SRDSCR2_SEIC_MASK,
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SRDSCR2_SEIC_SATA);
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/* Configure SRDSCR3 */
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out_be32(&priv->regs->srdscr3,
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SRDSCR3_KFR_SATA | SRDSCR3_KPH_SATA |
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SRDSCR3_SDFM_SATA_PEX | SRDSCR3_SDTXL_SATA);
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/* Configure SRDSCR4 */
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out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SATA);
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}
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/**
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* setup_pex() - Configure the SerDes device to PCI Express mode
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* @dev: The device to configure
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* @type: The PCI Express type to configure for (x1 or x2)
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*/
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static void setup_pex(struct udevice *dev, enum pex_type type)
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{
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struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
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/* Configure SRDSCR1 */
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setbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
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/* Configure SRDSCR2 */
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clrsetbits_be32(&priv->regs->srdscr2,
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SRDSCR2_SEIC_MASK,
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SRDSCR2_SEIC_PEX);
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/* Configure SRDSCR3 */
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out_be32(&priv->regs->srdscr3, SRDSCR3_SDFM_SATA_PEX);
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/* Configure SRDSCR4 */
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if (type == PEX_X2)
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out_be32(&priv->regs->srdscr4,
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priv->rfcks | SRDSCR4_PROT_PEX | SRDSCR4_PLANE_X2);
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else
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out_be32(&priv->regs->srdscr4,
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priv->rfcks | SRDSCR4_PROT_PEX);
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}
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/**
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* setup_sgmii() - Configure the SerDes device to SGMII mode
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* @dev: The device to configure
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*/
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static void setup_sgmii(struct udevice *dev)
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{
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struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
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/* Configure SRDSCR1 */
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clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
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/* Configure SRDSCR2 */
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clrsetbits_be32(&priv->regs->srdscr2,
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SRDSCR2_SEIC_MASK,
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SRDSCR2_SEIC_SGMII);
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/* Configure SRDSCR3 */
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out_be32(&priv->regs->srdscr3, 0);
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/* Configure SRDSCR4 */
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out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SGMII);
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}
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static int mpc83xx_serdes_probe(struct udevice *dev)
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{
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struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
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bool vdd;
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const char *proto;
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priv->regs = map_sysmem(dev_read_addr(dev),
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sizeof(struct mpc83xx_serdes_regs));
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switch (dev_read_u32_default(dev, "serdes-clk", -1)) {
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case 100:
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priv->rfcks = SRDSCR4_RFCKS_100;
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break;
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case 125:
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priv->rfcks = SRDSCR4_RFCKS_125;
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break;
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case 150:
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priv->rfcks = SRDSCR4_RFCKS_150;
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break;
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default:
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debug("%s: Could not read serdes clock value\n", dev->name);
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return -EINVAL;
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}
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vdd = dev_read_bool(dev, "vdd");
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/* 1.0V corevdd */
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if (vdd) {
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/* DPPE/DPPA = 0 */
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clrbits_be32(&priv->regs->srdscr0, SRDSCR0_DPP_1V2);
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/* VDD = 0 */
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clrbits_be32(&priv->regs->srdscr0, SRDSCR2_VDD_1V2);
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}
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proto = dev_read_string(dev, "proto");
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/* protocol specific configuration */
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if (!strcmp(proto, "sata")) {
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setup_sata(dev);
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} else if (!strcmp(proto, "pex")) {
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setup_pex(dev, PEX_X1);
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} else if (!strcmp(proto, "pex-x2")) {
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setup_pex(dev, PEX_X2);
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} else if (!strcmp(proto, "sgmii")) {
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setup_sgmii(dev);
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} else {
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debug("%s: Invalid protocol value %s\n", dev->name, proto);
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return -EINVAL;
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}
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/* Do a software reset */
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setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_RST);
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return 0;
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}
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static const struct udevice_id mpc83xx_serdes_ids[] = {
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{ .compatible = "fsl,mpc83xx-serdes" },
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{ }
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};
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U_BOOT_DRIVER(mpc83xx_serdes) = {
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.name = "mpc83xx_serdes",
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.id = UCLASS_MISC,
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.of_match = mpc83xx_serdes_ids,
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.probe = mpc83xx_serdes_probe,
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.priv_auto_alloc_size = sizeof(struct mpc83xx_serdes_priv),
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};
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232
drivers/misc/mpc83xx_serdes.h
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232
drivers/misc/mpc83xx_serdes.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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/**
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* enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
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* @SRDSCR0_DPPA: Bitmask for the DPPA (diff pk-pk swing for lane A)
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* field of the SRCSCR0
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* @SRDSCR0_DPPE: Bitmask for the DPPE (diff pk-pk swing for lane E)
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* field of the SRCSCR0
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* @SRDSCR0_DPP_1V2: Combined bitmask to set diff pk-pk swing for both lanes
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* @SRDSCR0_TXEQA_MASK: Bitmask for the TXEQA (transmit equalization for
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* lane A) field of the SRCSCR0
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* @SRDSCR0_TXEQA_SATA: Bitmask to set the TXEQA to the value used for SATA
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* @SRDSCR0_TXEQE_MASK: Bitmask for the TXEQE (transmit equalization for
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* lane E) field of the SRCSCR0
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* @SRDSCR0_TXEQE_SATA: Bitmask to set the TXEQE to the value used for SATA
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*/
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enum srdscr0_mask {
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SRDSCR0_DPPA = BIT(31 - 16),
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SRDSCR0_DPPE = BIT(31 - 20),
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SRDSCR0_DPP_1V2 = SRDSCR0_DPPE | SRDSCR0_DPPA,
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SRDSCR0_TXEQA_MASK = 0x00007000,
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SRDSCR0_TXEQA_SATA = 0x00001000,
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SRDSCR0_TXEQE_MASK = 0x00000700,
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SRDSCR0_TXEQE_SATA = 0x00000100,
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};
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/**
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* enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1)
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* @SRDSCR1_PLLBW: Bitmask for the PLLBW (PLL bandwidth) field of SRDSCR1
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*/
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enum srdscr1_mask {
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SRDSCR1_PLLBW = BIT(31 - 25),
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};
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/**
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* enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2)
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* @SRDSCR2_VDD_1V2: Bit mask to to set the VDD field of the SCRSCR2
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* @SRDSCR2_SEICA_MASK: Bitmask for the SEICA (Receiver electrical idle
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* detection control for lane A) field of the SRCSCR2
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* @SRDSCR2_SEICE_MASK: Bitmask for the SEICE (Receiver electrical idle
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* detection control for lane E) field of the SRCSCR2
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* @SRDSCR2_SEIC_MASK: Combined bitmask to set the receiver electrical idle
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* detection control for both lanes
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* @SRDSCR2_SEICA_SATA: Bitmask to set the SEICA field to the value used for
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* SATA
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* @SRDSCR2_SEICE_SATA: Bitmask to set the SEICE field to the value used for
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* SATA
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* @SRDSCR2_SEIC_SATA: Combined bitmask to set the value of both SEIC fields
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* to the value used for SATA
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* @SRDSCR2_SEICA_PEX: Bitmask to set the SEICA field to the value used for
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* PCI Express
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* @SRDSCR2_SEICE_PEX: Bitmask to set the SEICE field to the value used for
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* PCI Express
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* @SRDSCR2_SEIC_PEX: Combined bitmask to set the value of both SEIC fields
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* to the value used for PCI Express
|
||||||
|
* @SRDSCR2_SEICA_SGMII: Bitmask to set the SEICA field to the value used for
|
||||||
|
* SGMII
|
||||||
|
* @SRDSCR2_SEICE_SGMII: Bitmask to set the SEICE field to the value used for
|
||||||
|
* SGMII
|
||||||
|
* @SRDSCR2_SEIC_SGMII: Combined bitmask to set the value of both SEIC fields
|
||||||
|
* to the value used for SGMII
|
||||||
|
*/
|
||||||
|
enum srdscr2_mask {
|
||||||
|
SRDSCR2_VDD_1V2 = 0x00800000,
|
||||||
|
|
||||||
|
SRDSCR2_SEICA_MASK = 0x00001c00,
|
||||||
|
SRDSCR2_SEICE_MASK = 0x0000001c,
|
||||||
|
SRDSCR2_SEIC_MASK = SRDSCR2_SEICA_MASK | SRDSCR2_SEICE_MASK,
|
||||||
|
|
||||||
|
SRDSCR2_SEICA_SATA = 0x00001400,
|
||||||
|
SRDSCR2_SEICE_SATA = 0x00000014,
|
||||||
|
SRDSCR2_SEIC_SATA = SRDSCR2_SEICA_SATA | SRDSCR2_SEICE_SATA,
|
||||||
|
|
||||||
|
SRDSCR2_SEICA_PEX = 0x00001000,
|
||||||
|
SRDSCR2_SEICE_PEX = 0x00000010,
|
||||||
|
SRDSCR2_SEIC_PEX = SRDSCR2_SEICA_PEX | SRDSCR2_SEICE_PEX,
|
||||||
|
|
||||||
|
SRDSCR2_SEICA_SGMII = 0x00000100,
|
||||||
|
SRDSCR2_SEICE_SGMII = 0x00000001,
|
||||||
|
SRDSCR2_SEIC_SGMII = SRDSCR2_SEICA_SGMII | SRDSCR2_SEICE_SGMII,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* enum srdscr3_mask - Bit masks for SRDSCR3 (SerDes Control Register 3)
|
||||||
|
* @SRDSCR3_KFRA_SATA: Bitmask to set the KFRA field of SRDSCR3 to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR3_KFRE_SATA: Bitmask to set the KFRE field of SRDSCR3 to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR3_KFR_SATA: Combined bitmask to set both KFR fields to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR3_KPHA_SATA: Bitmask to set the KPHA field of SRDSCR3 to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR3_KPHE_SATA: Bitmask to set the KPHE field of SRDSCR3 to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR3_KPH_SATA: Combined bitmask to set both KPH fields to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR3_SDFMA_SATA_PEX: Bitmask to set the SDFMA field of SRDSCR3 to the
|
||||||
|
* value used by SATA and PCI Express
|
||||||
|
* @SRDSCR3_SDFME_SATA_PEX: Bitmask to set the SDFME field of SRDSCR3 to the
|
||||||
|
* value used by SATA and PCI Express
|
||||||
|
* @SRDSCR3_SDFM_SATA_PEX: Combined bitmask to set both SDFM fields to the
|
||||||
|
* value used by SATA and PCI Express
|
||||||
|
* @SRDSCR3_SDTXLA_SATA: Bitmask to set the SDTXLA field of SRDSCR3 to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR3_SDTXLE_SATA: Bitmask to set the SDTXLE field of SRDSCR3 to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR3_SDTXL_SATA: Combined bitmask to set both SDTXL fields to the
|
||||||
|
* value used by SATA
|
||||||
|
*
|
||||||
|
* KFRA = 'Kfr' gain selection in the CDR for lane A
|
||||||
|
* KFRE = 'Kfr' gain selection in the CDR for lane E
|
||||||
|
* SDFMA = Bandwidth of digital filter for lane A
|
||||||
|
* SDFME = Bandwidth of digital filter for lane E
|
||||||
|
* SDTXLA = Lane A transmitter amplitude levels
|
||||||
|
* SDTXLE = Lane E transmitter amplitude levels
|
||||||
|
*/
|
||||||
|
enum srdscr3_mask {
|
||||||
|
SRDSCR3_KFRA_SATA = 0x10000000,
|
||||||
|
SRDSCR3_KFRE_SATA = 0x00100000,
|
||||||
|
SRDSCR3_KFR_SATA = SRDSCR3_KFRA_SATA | SRDSCR3_KFRE_SATA,
|
||||||
|
|
||||||
|
SRDSCR3_KPHA_SATA = 0x04000000,
|
||||||
|
SRDSCR3_KPHE_SATA = 0x00040000,
|
||||||
|
SRDSCR3_KPH_SATA = SRDSCR3_KPHA_SATA | SRDSCR3_KPHE_SATA,
|
||||||
|
|
||||||
|
SRDSCR3_SDFMA_SATA_PEX = 0x01000000,
|
||||||
|
SRDSCR3_SDFME_SATA_PEX = 0x00010000,
|
||||||
|
SRDSCR3_SDFM_SATA_PEX = SRDSCR3_SDFMA_SATA_PEX | SRDSCR3_SDFME_SATA_PEX,
|
||||||
|
|
||||||
|
SRDSCR3_SDTXLA_SATA = 0x00000500,
|
||||||
|
SRDSCR3_SDTXLE_SATA = 0x00000005,
|
||||||
|
SRDSCR3_SDTXL_SATA = SRDSCR3_SDTXLA_SATA | SRDSCR3_SDTXLE_SATA,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* enum srdscr4_mask - Bit masks for SRDSCR4 (SerDes Control Register 4)
|
||||||
|
* @SRDSCR4_PROTA_SATA: Bitmask to set the PROTA field of SRDSCR4 to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR4_PROTE_SATA: Bitmask to set the PROTE field of SRDSCR4 to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR4_PROT_SATA: Combined bitmask to set both PROT fields to the
|
||||||
|
* value used by SATA
|
||||||
|
* @SRDSCR4_PROTA_PEX: Bitmask to set the PROTA field of SRDSCR4 to the
|
||||||
|
* value used by PCI Express
|
||||||
|
* @SRDSCR4_PROTE_PEX: Bitmask to set the PROTE field of SRDSCR4 to the
|
||||||
|
* value used by PCI Express
|
||||||
|
* @SRDSCR4_PROT_PEX: Combined bitmask to set both PROT fields to the
|
||||||
|
* value used by PCI Express
|
||||||
|
* @SRDSCR4_PROTA_SGMII: Bitmask to set the PROTA field of SRDSCR4 to the
|
||||||
|
* value used by SGMII
|
||||||
|
* @SRDSCR4_PROTE_SGMII: Bitmask to set the PROTE field of SRDSCR4 to the
|
||||||
|
* value used by SGMII
|
||||||
|
* @SRDSCR4_PROT_SGMII: Combined bitmask to set both PROT fields to the
|
||||||
|
* value used by SGMII
|
||||||
|
* @SRDSCR4_PLANE_X2: Bitmask to set the PLANE field of SRDSCR4
|
||||||
|
* @SRDSCR4_RFCKS_100: Bitmask to set the RFCKS field of SRDSCR4 to the
|
||||||
|
* value 100Mhz
|
||||||
|
* @SRDSCR4_RFCKS_125: Bitmask to set the RFCKS field of SRDSCR4 to the
|
||||||
|
* value 125Mhz
|
||||||
|
* @SRDSCR4_RFCKS_150: Bitmask to set the RFCKS field of SRDSCR4 to the
|
||||||
|
* value 150Mhz
|
||||||
|
*
|
||||||
|
* PROTA = Lane A protocol select
|
||||||
|
* PROTE = Lane E protocol select
|
||||||
|
* PLAME = Number of PCI Express lanes
|
||||||
|
*/
|
||||||
|
enum srdscr4_mask {
|
||||||
|
SRDSCR4_PROTA_SATA = 0x00000800,
|
||||||
|
SRDSCR4_PROTE_SATA = 0x00000008,
|
||||||
|
SRDSCR4_PROT_SATA = SRDSCR4_PROTA_SATA | SRDSCR4_PROTE_SATA,
|
||||||
|
|
||||||
|
SRDSCR4_PROTA_PEX = 0x00000100,
|
||||||
|
SRDSCR4_PROTE_PEX = 0x00000001,
|
||||||
|
SRDSCR4_PROT_PEX = SRDSCR4_PROTA_PEX | SRDSCR4_PROTE_PEX,
|
||||||
|
|
||||||
|
SRDSCR4_PROTA_SGMII = 0x00000500,
|
||||||
|
SRDSCR4_PROTE_SGMII = 0x00000005,
|
||||||
|
SRDSCR4_PROT_SGMII = SRDSCR4_PROTA_SGMII | SRDSCR4_PROTE_SGMII,
|
||||||
|
|
||||||
|
SRDSCR4_PLANE_X2 = 0x01000000,
|
||||||
|
|
||||||
|
SRDSCR4_RFCKS_100 = (0 << 28),
|
||||||
|
SRDSCR4_RFCKS_125 = (1 << 28),
|
||||||
|
SRDSCR4_RFCKS_150 = (3 << 28),
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* enum srdsrstctl_mask - Bit masks for SRDSRSTCTL (SerDes Reset Control Register)
|
||||||
|
* @SRDSRSTCTL_RST: Bitmask for the RST (Software reset) field of the
|
||||||
|
* SRDSRSTCTL
|
||||||
|
* @SRDSRSTCTL_SATA_RESET: Bitmask for the SATA_RESET (SATA reset) field of the
|
||||||
|
* SRDSRSTCTL
|
||||||
|
*/
|
||||||
|
enum srdsrstctl_mask {
|
||||||
|
SRDSRSTCTL_RST = 0x80000000,
|
||||||
|
SRDSRSTCTL_SATA_RESET = 0xf,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct mpc83xx_serdes_regs - Register map of the SerDes controller
|
||||||
|
* @srdscr0: SerDes Control Register 0
|
||||||
|
* @srdscr1: SerDes Control Register 1
|
||||||
|
* @srdscr2: SerDes Control Register 2
|
||||||
|
* @srdscr3: SerDes Control Register 3
|
||||||
|
* @srdscr4: SerDes Control Register 4
|
||||||
|
* @fill0: Reserved space in the register map
|
||||||
|
* @srdsrstctl: SerDes Reset Control Register
|
||||||
|
*/
|
||||||
|
struct mpc83xx_serdes_regs {
|
||||||
|
u32 srdscr0;
|
||||||
|
u32 srdscr1;
|
||||||
|
u32 srdscr2;
|
||||||
|
u32 srdscr3;
|
||||||
|
u32 srdscr4;
|
||||||
|
u8 fill0[12];
|
||||||
|
u32 srdsrstctl;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* enum pex_type - Types of PCI Express
|
||||||
|
* @PEX_X1: PCI Express in x1 mode
|
||||||
|
* @PEX_X2: PCI Express in x2 mode
|
||||||
|
*/
|
||||||
|
enum pex_type {
|
||||||
|
PEX_X1,
|
||||||
|
PEX_X2,
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue
Block a user