Fix and optimize MII operations on FEC (MPC8xx) controllers
This patch fixes several issues at least on a MPC885 based system with two FEC interfaces used in MII mode. 1. PHY discovery should first read PHY_PHYIDR2 register and only then PHY_PHYIDR1 like cpu/mpc8xx/fec.c::mii_discover_phy() does it, otherwise the values read are wrong. Also notice, that PHY discovery cannot work on MPC88x / MPC87x in setups with both FECs active at all in its present form, because for both interfaces the registers from FEC 1 are used to communicate over MII. 2. Remove code duplication for resetting the FEC by isolating it into a separate function. 3. Initialize MII on FEC 1 when communicating over FEC 2 in fec_init(). 4. Optimize mii_init() to only reset the FEC 1 controller once. 5. Fix a typo in mii_init() using index i instead of j thus potentially leading to unpredictable results. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
This commit is contained in:
Guennadi Liakhovetski
Wolfgang Denk
parent
6a5e1d75bf
commit
d197ffd817
107
cpu/mpc8xx/fec.c
107
cpu/mpc8xx/fec.c
@ -143,6 +143,7 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length);
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static int fec_recv(struct eth_device* dev);
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static int fec_init(struct eth_device* dev, bd_t * bd);
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static void fec_halt(struct eth_device* dev);
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static void __mii_init(void);
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int fec_initialize(bd_t *bis)
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{
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@ -539,6 +540,30 @@ static void fec_pin_init(int fecidx)
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}
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}
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static int fec_reset(volatile fec_t *fecp)
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{
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int i;
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/* Whack a reset.
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* A delay is required between a reset of the FEC block and
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* initialization of other FEC registers because the reset takes
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* some time to complete. If you don't delay, subsequent writes
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* to FEC registers might get killed by the reset routine which is
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* still in progress.
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*/
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fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
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for (i = 0;
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(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
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++i) {
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udelay (1);
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}
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if (i == FEC_RESET_DELAY)
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return -1;
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return 0;
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}
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static int fec_init (struct eth_device *dev, bd_t * bd)
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{
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struct ether_fcc_info_s *efis = dev->priv;
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@ -573,23 +598,17 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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#endif /* CONFIG_FADS */
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}
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/* Whack a reset.
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* A delay is required between a reset of the FEC block and
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* initialization of other FEC registers because the reset takes
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* some time to complete. If you don't delay, subsequent writes
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* to FEC registers might get killed by the reset routine which is
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* still in progress.
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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/* the MII interface is connected to FEC1
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* so for the miiphy_xxx function to work we must
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* call mii_init since fec_halt messes the thing up
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*/
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fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
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for (i = 0;
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(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
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++i) {
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udelay (1);
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}
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if (i == FEC_RESET_DELAY) {
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if (efis->ether_index != 0)
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__mii_init();
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#endif
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if (fec_reset(fecp) < 0)
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printf ("FEC_RESET_DELAY timeout\n");
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return 0;
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}
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/* We use strictly polling mode only
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*/
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@ -603,7 +622,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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/* Set station address
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*/
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#define ea eth_get_dev()->enetaddr
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#define ea dev->enetaddr
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fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
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fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
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#undef ea
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@ -716,15 +735,8 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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} else {
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efis->actual_phy_addr = efis->phy_addr;
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}
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#if defined(CONFIG_MII) && defined(CONFIG_RMII)
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/* the MII interface is connected to FEC1
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* so for the miiphy_xxx function to work we must
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* call mii_init since fec_halt messes the thing up
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*/
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if (efis->ether_index != 0)
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mii_init();
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/*
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* adapt the RMII speed to the speed of the phy
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*/
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@ -874,15 +886,14 @@ static int mii_discover_phy(struct eth_device *dev)
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udelay(10000); /* wait 10ms */
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}
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for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
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phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
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phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
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#ifdef ET_DEBUG
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printf("PHY type 0x%x pass %d type ", phytype, pass);
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#endif
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if (phytype != 0xffff) {
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phyaddr = phyno;
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phytype <<= 16;
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phytype |= mii_send(mk_mii_read(phyno,
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PHY_PHYIDR2));
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PHY_PHYIDR1)) << 16;
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#ifdef ET_DEBUG
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printf("PHY @ 0x%x pass %d type ",phyno,pass);
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@ -929,36 +940,17 @@ static int mii_discover_phy(struct eth_device *dev)
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#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
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/****************************************************************************
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* mii_init -- Initialize the MII for MII command without ethernet
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* mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
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* This function is a subset of eth_init
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****************************************************************************
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*/
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void mii_init (void)
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static void __mii_init(void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
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int i, j;
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for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) {
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/* Whack a reset.
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* A delay is required between a reset of the FEC block and
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* initialization of other FEC registers because the reset takes
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* some time to complete. If you don't delay, subsequent writes
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* to FEC registers might get killed by the reset routine which is
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* still in progress.
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*/
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fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
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for (i = 0;
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(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
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++i) {
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udelay (1);
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}
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if (i == FEC_RESET_DELAY) {
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if (fec_reset(fecp) < 0)
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printf ("FEC_RESET_DELAY timeout\n");
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return;
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}
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/* We use strictly polling mode only
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*/
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@ -968,14 +960,21 @@ void mii_init (void)
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*/
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fecp->fec_ievent = 0xffc0;
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/* Setup the pin configuration of the FEC(s)
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*/
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fec_pin_init(ether_fcc_info[i].ether_index);
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/* Now enable the transmit and receive processing
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*/
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fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
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}
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}
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void mii_init (void)
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{
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int i;
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__mii_init();
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/* Setup the pin configuration of the FEC(s)
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*/
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for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
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fec_pin_init(ether_fcc_info[i].ether_index);
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}
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/*****************************************************************************
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