serial: UniPhier: use 32 bit register access
For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11) is not working correctly. As a side effect, it also modifies MCR register (offset = 0x10) and results in unexpected behavior. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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c8bc166124
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (C) 2012-2014 Panasonic Corporation
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* Copyright (C) 2012-2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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@ -13,31 +13,25 @@
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#include <serial.h>
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#include <serial.h>
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#include <fdtdec.h>
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#include <fdtdec.h>
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#define UART_REG(x) \
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u8 x; \
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u8 postpad_##x[3];
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/*
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/*
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* Note: Register map is slightly different from that of 16550.
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* Note: Register map is slightly different from that of 16550.
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*/
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*/
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struct uniphier_serial {
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struct uniphier_serial {
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UART_REG(rbr); /* 0x00 */
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u32 rx; /* In: Receive buffer */
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UART_REG(ier); /* 0x04 */
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#define tx rx /* Out: Transmit buffer */
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UART_REG(iir); /* 0x08 */
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u32 ier; /* Interrupt Enable Register */
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UART_REG(fcr); /* 0x0c */
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u32 iir; /* In: Interrupt ID Register */
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u8 mcr; /* 0x10 */
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u32 char_fcr; /* Charactor / FIFO Control Register */
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u8 lcr;
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u32 lcr_mcr; /* Line/Modem Control Register */
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u16 __postpad;
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#define LCR_SHIFT 8
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UART_REG(lsr); /* 0x14 */
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#define LCR_MASK (0xff << (LCR_SHIFT))
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UART_REG(msr); /* 0x18 */
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u32 lsr; /* In: Line Status Register */
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u32 __none1;
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u32 msr; /* In: Modem Status Register */
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u32 __none2;
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u32 __rsv0;
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u16 dlr;
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u32 __rsv1;
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u16 __postpad2;
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u32 dlr; /* Divisor Latch Register */
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};
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};
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#define thr rbr
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struct uniphier_serial_private_data {
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struct uniphier_serial_private_data {
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struct uniphier_serial __iomem *membase;
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struct uniphier_serial __iomem *membase;
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};
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};
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@ -51,12 +45,16 @@ static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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const unsigned int mode_x_div = 16;
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const unsigned int mode_x_div = 16;
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unsigned int divisor;
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unsigned int divisor;
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u32 tmp;
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writeb(UART_LCR_WLEN8, &port->lcr);
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tmp = readl(&port->lcr_mcr);
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tmp &= ~LCR_MASK;
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tmp |= UART_LCR_WLEN8 << LCR_SHIFT;
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writel(tmp, &port->lcr_mcr);
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divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
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divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
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writew(divisor, &port->dlr);
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writel(divisor, &port->dlr);
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return 0;
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return 0;
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}
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}
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@ -65,20 +63,20 @@ static int uniphier_serial_getc(struct udevice *dev)
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{
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{
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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if (!(readb(&port->lsr) & UART_LSR_DR))
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if (!(readl(&port->lsr) & UART_LSR_DR))
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return -EAGAIN;
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return -EAGAIN;
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return readb(&port->rbr);
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return readl(&port->rx);
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}
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}
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static int uniphier_serial_putc(struct udevice *dev, const char c)
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static int uniphier_serial_putc(struct udevice *dev, const char c)
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{
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{
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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if (!(readb(&port->lsr) & UART_LSR_THRE))
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if (!(readl(&port->lsr) & UART_LSR_THRE))
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return -EAGAIN;
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return -EAGAIN;
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writeb(c, &port->thr);
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writel(c, &port->tx);
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return 0;
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return 0;
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}
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}
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@ -88,9 +86,9 @@ static int uniphier_serial_pending(struct udevice *dev, bool input)
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
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if (input)
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if (input)
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return readb(&port->lsr) & UART_LSR_DR;
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return readl(&port->lsr) & UART_LSR_DR;
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else
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else
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return !(readb(&port->lsr) & UART_LSR_THRE);
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return !(readl(&port->lsr) & UART_LSR_THRE);
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}
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}
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static int uniphier_serial_probe(struct udevice *dev)
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static int uniphier_serial_probe(struct udevice *dev)
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