ARM: fix s3c2410 timer code
This patch fixes the s3c24x0 timer code to work with the ARM relocation feature. Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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@ -35,19 +35,7 @@
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#include <asm/io.h>
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#include <asm/arch/s3c24x0_cpu.h>
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int timer_load_val = 0;
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static ulong timer_clk;
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/* macro to read the 16 bit timer */
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static inline ulong READ_TIMER(void)
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{
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struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
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return readl(&timers->tcnto4) & 0xffff;
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}
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static ulong timestamp;
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static ulong lastdec;
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DECLARE_GLOBAL_DATA_PTR;
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int timer_init(void)
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{
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@ -57,27 +45,27 @@ int timer_init(void)
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/* use PWM Timer 4 because it has no output */
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/* prescaler for Timer 4 is 16 */
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writel(0x0f00, &timers->tcfg0);
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if (timer_load_val == 0) {
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if (gd->tbu == 0) {
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/*
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* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
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* (default) and prescaler = 16. Should be 10390
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* @33.25MHz and 15625 @ 50 MHz
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*/
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timer_load_val = get_PCLK() / (2 * 16 * 100);
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timer_clk = get_PCLK() / (2 * 16);
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gd->tbu = get_PCLK() / (2 * 16 * 100);
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gd->timer_rate_hz = get_PCLK() / (2 * 16);
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}
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/* load value for 10 ms timeout */
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lastdec = timer_load_val;
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writel(timer_load_val, &timers->tcntb4);
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writel(gd->tbu, &timers->tcntb4);
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/* auto load, manual update of timer 4 */
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tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
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writel(tmr, &timers->tcon);
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/* auto load, start timer 4 */
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tmr = (tmr & ~0x0700000) | 0x0500000;
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writel(tmr, &timers->tcon);
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timestamp = 0;
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gd->lastinc = 0;
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gd->tbl = 0;
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return (0);
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return 0;
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}
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/*
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@ -94,7 +82,7 @@ void __udelay (unsigned long usec)
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ulong start = get_ticks();
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tmo = usec / 1000;
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tmo *= (timer_load_val * 100);
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tmo *= (gd->tbu * 100);
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tmo /= 1000;
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while ((ulong) (get_ticks() - start) < tmo)
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@ -105,7 +93,7 @@ ulong get_timer_masked(void)
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{
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ulong tmr = get_ticks();
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return tmr / (timer_clk / CONFIG_SYS_HZ);
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return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ);
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}
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void udelay_masked(unsigned long usec)
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@ -116,10 +104,10 @@ void udelay_masked(unsigned long usec)
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= (timer_load_val * 100);
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tmo *= (gd->tbu * 100);
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tmo /= 1000;
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} else {
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tmo = usec * (timer_load_val * 100);
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tmo = usec * (gd->tbu * 100);
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tmo /= (1000 * 1000);
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}
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@ -137,18 +125,19 @@ void udelay_masked(unsigned long usec)
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*/
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unsigned long long get_ticks(void)
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{
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ulong now = READ_TIMER();
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struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
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ulong now = readl(&timers->tcnto4) & 0xffff;
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if (lastdec >= now) {
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if (gd->lastinc >= now) {
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/* normal mode */
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timestamp += lastdec - now;
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gd->tbl += gd->lastinc - now;
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} else {
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/* we have an overflow ... */
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timestamp += lastdec + timer_load_val - now;
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gd->tbl += gd->lastinc + gd->tbu - now;
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}
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lastdec = now;
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gd->lastinc = now;
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return timestamp;
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return gd->tbl;
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}
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/*
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@ -157,20 +146,7 @@ unsigned long long get_ticks(void)
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*/
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ulong get_tbclk(void)
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{
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ulong tbclk;
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#if defined(CONFIG_SMDK2400)
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tbclk = timer_load_val * 100;
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#elif defined(CONFIG_SBC2410X) || \
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defined(CONFIG_SMDK2410) || \
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defined(CONFIG_S3C2440) || \
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defined(CONFIG_VCMA9)
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tbclk = CONFIG_SYS_HZ;
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#else
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# error "tbclk not configured"
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#endif
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return tbclk;
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return CONFIG_SYS_HZ;
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}
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/*
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