imx: add cpu type for i.MX6QP/DP
Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
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@ -62,12 +62,12 @@ u32 get_cpu_rev(void)
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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u32 reg = readl(&anatop->digprog_sololite);
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u32 type = ((reg >> 16) & 0xff);
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u32 major;
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u32 major, cfg = 0;
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if (type != MXC_CPU_MX6SL) {
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reg = readl(&anatop->digprog);
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struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
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u32 cfg = readl(&scu->config) & 3;
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cfg = readl(&scu->config) & 3;
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type = ((reg >> 16) & 0xff);
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if (type == MXC_CPU_MX6DL) {
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if (!cfg)
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@ -81,6 +81,13 @@ u32 get_cpu_rev(void)
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}
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major = ((reg >> 8) & 0xff);
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if ((major >= 1) &&
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((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
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major--;
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type = MXC_CPU_MX6QP;
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if (cfg == 1)
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type = MXC_CPU_MX6DP;
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}
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reg &= 0xff; /* mx6 silicon revision */
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return (type << 12) | (reg + (0x10 * (major + 1)));
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}
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@ -122,6 +122,10 @@ unsigned imx_ddr_size(void)
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const char *get_imx_type(u32 imxtype)
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{
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switch (imxtype) {
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case MXC_CPU_MX6QP:
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return "6QP"; /* Quad-Plus version of the mx6 */
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case MXC_CPU_MX6DP:
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return "6DP"; /* Dual-Plus version of the mx6 */
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case MXC_CPU_MX6Q:
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return "6Q"; /* Quad-core version of the mx6 */
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case MXC_CPU_MX6D:
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@ -12,6 +12,8 @@
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#define MXC_CPU_MX6Q 0x63
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#define MXC_CPU_MX6D 0x64
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#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
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#define MXC_CPU_MX6DP 0x68
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#define MXC_CPU_MX6QP 0x69
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#define CS0_128 0
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#define CS0_64M_CS1_64M 1
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@ -30,9 +30,7 @@ const char *get_imx_type(u32 imxtype);
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unsigned imx_ddr_size(void);
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void set_chipselect_size(int const);
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#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
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is_cpu_type(MXC_CPU_MX6D)) && \
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(soc_rev() >= CHIP_REV_2_0))
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#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
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/*
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* Initializes on-chip ethernet controllers.
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