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arch: arm: fsl: Add XHCI support for LS1021A

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Add base register address information for USB
XHCI controller on LS1021A

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
This commit is contained in:
Ramneek Mehresh 2015-05-29 14:47:20 +05:30 committed by Marek Vasut
parent ba92ee06a5
commit d09e401b43
2 changed files with 11 additions and 0 deletions
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1
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -35,6 +35,7 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)

10
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View File

@ -396,4 +396,14 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
/* USB-XHCI */
#define FSL_XHCI_BASE 0x3100000
#define FSL_OCP1_SCP_BASE 0x4a084c00
#define FSL_OTG_WRAPPER_BASE 0x4A020000
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */