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Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR

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We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2018-04-18 13:50:47 -04:00
parent f1b1f77060
commit d024236e5a
362 changed files with 0 additions and 717 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
api/api_net.c
View File

@ -12,8 +12,6 @@
#include <linux/types.h>
#include <api_public.h>
DECLARE_GLOBAL_DATA_PTR;
#define DEBUG
#undef DEBUG

2
arch/arm/cpu/arm1136/mx31/timer.c
View File

@ -23,8 +23,6 @@
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
DECLARE_GLOBAL_DATA_PTR;
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{

2
arch/arm/cpu/arm1136/mx35/timer.c
View File

@ -12,8 +12,6 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
DECLARE_GLOBAL_DATA_PTR;
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */

2
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -26,8 +26,6 @@
#endif
#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);

2
arch/arm/cpu/armv8/s32v234/cpu.c
View File

@ -12,8 +12,6 @@
#include <asm/arch/mc_me_regs.h>
#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
u32 cpu_mask(void)
{
return readl(MC_ME_CS);

2
arch/arm/cpu/pxa/timer.c
View File

@ -9,8 +9,6 @@
#include <common.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int timer_init(void)
{
writel(0, CONFIG_SYS_TIMER_COUNTER);

2
arch/arm/include/asm/arch-omap4/sys_proto.h
View File

@ -16,8 +16,6 @@
#include <asm/arch/mux_omap4.h>
#include <asm/ti-common/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;

2
arch/arm/include/asm/arch-omap5/sys_proto.h
View File

@ -16,8 +16,6 @@
#include <asm/arch/clock.h>
#include <asm/ti-common/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Structure for Iodelay configuration registers.
* Theoretical max for g_delay is 21560 ps.

2
arch/arm/lib/cmd_boot.c
View File

@ -21,8 +21,6 @@
#include <common.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* ARMv7M does not support ARM instruction mode. However, the
* interworking BLX and BX instructions do encode the ARM/Thumb

2
arch/arm/mach-at91/spl_atmel.c
View File

@ -15,8 +15,6 @@
#include <asm/arch/clk.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
static void switch_to_main_crystal_osc(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

2
arch/arm/mach-davinci/spl.c
View File

@ -16,8 +16,6 @@
#include <spi_flash.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
void puts(const char *str)
{

2
arch/arm/mach-exynos/clock_init_exynos5.c
View File

@ -21,8 +21,6 @@
#define FSYS1_MMC0_DIV_MASK 0xff0f
#define FSYS1_MMC0_DIV_VAL 0x0701
DECLARE_GLOBAL_DATA_PTR;
struct arm_clk_ratios arm_clk_ratios[] = {
#ifdef CONFIG_EXYNOS5420
{

2
arch/arm/mach-exynos/mmu-arm64.c
View File

@ -8,8 +8,6 @@
#include <common.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_EXYNOS7420
static struct mm_region exynos7420_mem_map[] = {
{

2
arch/arm/mach-imx/cmd_dek.c
View File

@ -16,8 +16,6 @@
#include <asm/arch/clock.h>
#include <mapmem.h>
DECLARE_GLOBAL_DATA_PTR;
/**
* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
* @src: - Address of data to be encapsulated

2
arch/arm/mach-imx/mx7ulp/pcc.c
View File

@ -12,8 +12,6 @@
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define PCC_CLKSRC_TYPES 2
#define PCC_CLKSRC_NUM 7

2
arch/arm/mach-imx/mx7ulp/scg.c
View File

@ -12,8 +12,6 @@
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
scg_p scg1_regs = (scg_p)SCG1_RBASE;
static u32 scg_src_get_rate(enum scg_clk clksrc)

2
arch/arm/mach-imx/mx8m/clock.c
View File

@ -14,8 +14,6 @@
#include <errno.h>
#include <linux/iopoll.h>
DECLARE_GLOBAL_DATA_PTR;
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
static u32 decode_frac_pll(enum clk_root_src frac_pll)

2
arch/arm/mach-imx/mx8m/clock_slice.c
View File

@ -12,8 +12,6 @@
#include <asm/io.h>
#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
static struct clk_root_map root_array[] = {

2
arch/arm/mach-imx/timer.c
View File

@ -38,8 +38,6 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
#define GPTPR_PRESCALER24M_SHIFT 12
#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
DECLARE_GLOBAL_DATA_PTR;
static inline int gpt_has_clk_source_osc(void)
{
#if defined(CONFIG_MX6)

2
arch/arm/mach-mvebu/armada3700/cpu.c
View File

@ -14,8 +14,6 @@
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
/* Armada 3700 */
#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))

2
arch/arm/mach-mvebu/armada8k/cpu.c
View File

@ -14,8 +14,6 @@
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
/* Armada 7k/8k */
#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)

2
arch/arm/mach-mvebu/sata.c
View File

@ -8,8 +8,6 @@
#include <ahci.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Dummy implementation that can be overwritten by a board
* specific function

2
arch/arm/mach-mvebu/timer.c
View File

@ -11,8 +11,6 @@
#include <asm/io.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
#define TIMER_LOAD_VAL 0xffffffff
static int init_done __attribute__((section(".data"))) = 0;

2
arch/arm/mach-omap2/omap3/board.c
View File

@ -28,8 +28,6 @@
#include <asm/omap_common.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
/* Declarations */
extern omap3_sysinfo sysinfo;
#ifndef CONFIG_SYS_L2CACHE_OFF

2
arch/arm/mach-omap2/omap4/hwinit.c
View File

@ -21,8 +21,6 @@
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {

2
arch/arm/mach-omap2/omap5/hwinit.c
View File

@ -24,8 +24,6 @@
#include <asm/emif.h>
#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
#ifndef CONFIG_DM_GPIO

2
arch/arm/mach-rockchip/rk3036-board-spl.c
View File

@ -14,8 +14,6 @@
#include <asm/arch/timer.h>
#include <asm/arch/uart.h>
DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0x20008000
#define DEBUG_UART_BASE 0x20068000

2
arch/arm/mach-rockchip/rk3188-board.c
View File

@ -18,8 +18,6 @@
#include <asm/gpio.h>
#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;
int board_late_init(void)
{
struct rk3188_grf *grf;

2
arch/arm/mach-rockchip/rk322x-board-spl.c
View File

@ -21,8 +21,6 @@ u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0x11000000
#define SGRF_BASE 0x10140000

2
arch/arm/mach-rockchip/rk3288-board-tpl.c
View File

@ -19,8 +19,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xff770000
void board_init_f(ulong dummy)
{

2
arch/arm/mach-rockchip/rk3368-board-spl.c
View File

@ -17,8 +17,6 @@
#include <asm/arch/periph.h>
#include <asm/arch/timer.h>
DECLARE_GLOBAL_DATA_PTR;
void board_debug_uart_init(void)
{
}

2
arch/arm/mach-rockchip/rk3368-board-tpl.c
View File

@ -18,8 +18,6 @@
#include <asm/arch/timer.h>
#include <syscon.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
* secure mode (i.e. EL3) and an ATF will eventually be booted before

2
arch/arm/mach-rockchip/rk3399-board-spl.c
View File

@ -19,8 +19,6 @@
#include <spl.h>
#include <syscon.h>
DECLARE_GLOBAL_DATA_PTR;
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);

2
arch/arm/mach-socfpga/clock_manager_arria10.c
View File

@ -10,8 +10,6 @@
#include <dm.h>
#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static u32 eosc1_hz;
static u32 cb_intosc_hz;
static u32 f2s_free_hz;

2
arch/arm/mach-socfpga/clock_manager_gen5.c
View File

@ -10,8 +10,6 @@
#include <asm/arch/clock_manager.h>
#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;

2
arch/arm/mach-socfpga/fpga_manager.c
View File

@ -15,8 +15,6 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
DECLARE_GLOBAL_DATA_PTR;
/* Timeout count */
#define FPGA_TIMEOUT_CNT 0x1000000

2
arch/arm/mach-socfpga/freeze_controller.c
View File

@ -11,8 +11,6 @@
#include <asm/arch/freeze_controller.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_freeze_controller *freeze_controller_base =
(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);

2
arch/arm/mach-socfpga/misc_arria10.c
View File

@ -28,8 +28,6 @@
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;

2
arch/arm/mach-socfpga/reset_manager.c
View File

@ -9,8 +9,6 @@
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;

2
arch/arm/mach-socfpga/reset_manager_gen5.c
View File

@ -11,8 +11,6 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =

2
arch/arm/mach-socfpga/scan_manager.c
View File

@ -28,8 +28,6 @@
#define SCANMGR_STAT_ACTIVE (1 << 31)
#define SCANMGR_STAT_WFIFOCNT_MASK 0x70000000
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_scan_manager *scan_manager_base =
(void *)(SOCFPGA_SCANMGR_ADDRESS);
static const struct socfpga_freeze_controller *freeze_controller_base =

2
arch/arm/mach-socfpga/system_manager_gen5.c
View File

@ -9,8 +9,6 @@
#include <asm/arch/system_manager.h>
#include <asm/arch/fpga_manager.h>
DECLARE_GLOBAL_DATA_PTR;
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

1
arch/arm/mach-sunxi/board.c
View File

@ -209,7 +209,6 @@ void s_init(void)
}
#ifdef CONFIG_SPL_BUILD
DECLARE_GLOBAL_DATA_PTR;
#endif
/* The sunxi internal brom will try to loader external bootloader

2
arch/arm/mach-sunxi/dram_sun9i.c
View File

@ -20,8 +20,6 @@
#include <asm/arch/dram.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
/*

2
arch/arm/mach-tegra/board186.c
View File

@ -7,8 +7,6 @@
#include <common.h>
#include <asm/arch/tegra.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
return 0;

2
arch/arm/mach-tegra/tegra186/nvtboot_board.c
View File

@ -11,8 +11,6 @@
#include <asm/arch/tegra.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long nvtboot_boot_x0;
/*

2
arch/arm/mach-zynq/ddrc.c
View File

@ -10,8 +10,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_ZYNQ_DDRC_INIT
void zynq_ddrc_init(void) {}
#else

2
arch/arm/mach-zynq/spl.c
View File

@ -13,8 +13,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/ps7_init_gpl.h>
DECLARE_GLOBAL_DATA_PTR;
void board_init_f(ulong dummy)
{
ps7_init();

2
arch/microblaze/cpu/spl.c
View File

@ -12,8 +12,6 @@
#include <asm/io.h>
#include <asm/u-boot.h>
DECLARE_GLOBAL_DATA_PTR;
bool boot_linux;
u32 spl_boot_device(void)

2
arch/microblaze/lib/bootm.c
View File

@ -15,8 +15,6 @@
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
DECLARE_GLOBAL_DATA_PTR;
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{

2
arch/mips/mach-ath79/ar933x/ddr.c
View File

@ -12,8 +12,6 @@
#include <mach/ar71xx_regs.h>
#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
#define DDR_CTRL_UPD_EMR3S BIT(5)
#define DDR_CTRL_UPD_EMR2S BIT(4)
#define DDR_CTRL_PRECHARGE BIT(3)

2
arch/mips/mach-ath79/qca953x/ddr.c
View File

@ -12,8 +12,6 @@
#include <mach/ar71xx_regs.h>
#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
#define DDR_CTRL_UPD_EMR3S BIT(5)
#define DDR_CTRL_UPD_EMR2S BIT(4)
#define DDR_CTRL_PRECHARGE BIT(3)

2
arch/nds32/lib/boot.c
View File

@ -9,8 +9,6 @@
#include <common.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char * const argv[])
{

2
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -54,8 +54,6 @@
#include <fsl_qe.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
* For deriving usb clock from 100MHz sysclk, reference divisor is set

2
arch/powerpc/cpu/mpc86xx/fdt.c
View File

@ -9,8 +9,6 @@
#include <fdt_support.h>
#include <asm/mp.h>
DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);

2
arch/powerpc/lib/extable.c
View File

@ -21,8 +21,6 @@
* on our cache or tlb entries.
*/
DECLARE_GLOBAL_DATA_PTR;
struct exception_table_entry
{
unsigned long insn, fixup;

2
arch/powerpc/lib/spl.c
View File

@ -9,8 +9,6 @@
#include <image.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* This function jumps to an image with argument. Normally an FDT or ATAGS
* image.

2
arch/riscv/lib/boot.c
View File

@ -8,8 +8,6 @@
#include <common.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long do_go_exec(ulong (*entry)(int, char * const []),
int argc, char * const argv[])
{

2
arch/sandbox/lib/bootm.c
View File

@ -7,8 +7,6 @@
#include <common.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818
struct arm_z_header {

2
arch/x86/cpu/pci.c
View File

@ -17,8 +17,6 @@
#include <asm/io.h>
#include <asm/pci.h>
DECLARE_GLOBAL_DATA_PTR;
int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size)
{

2
arch/x86/cpu/qemu/cpu.c
View File

@ -11,8 +11,6 @@
#include <qfw.h>
#include <asm/cpu.h>
DECLARE_GLOBAL_DATA_PTR;
int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size)
{
if (size < CPU_MAX_NAME_LEN)

2
arch/x86/cpu/tangier/tangier.c
View File

@ -8,8 +8,6 @@
#include <asm/scu.h>
#include <asm/u-boot-x86.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initializations
*/

2
arch/x86/cpu/x86_64/cpu.c
View File

@ -8,8 +8,6 @@
#include <common.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
/* Global declaration of gd */
struct global_data *global_data_ptr;

2
arch/x86/lib/lpc-uclass.c
View File

@ -8,8 +8,6 @@
#include <common.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
UCLASS_DRIVER(lpc) = {
.id = UCLASS_LPC,
.name = "lpc",

2
arch/x86/lib/zimage.c
View File

@ -28,8 +28,6 @@
#include <linux/compiler.h>
#include <linux/libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Memory lay-out:
*

2
board/armadeus/opos6uldev/board.c
View File

@ -13,8 +13,6 @@
#include <asm/io.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_VIDEO_MXS
#define LCD_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \

2
board/astro/mcf5373l/fpga.c
View File

@ -25,8 +25,6 @@
#include <asm/io.h>
#include "fpga.h"
DECLARE_GLOBAL_DATA_PTR;
int altera_pre_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;

2
board/bachmann/ot1200/ot1200_spl.c
View File

@ -8,8 +8,6 @@
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
DECLARE_GLOBAL_DATA_PTR;
/* Configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */

2
board/barco/platinum/spl_picon.c
View File

@ -21,8 +21,6 @@
#include "platinum.h"
DECLARE_GLOBAL_DATA_PTR;
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */

2
board/barco/platinum/spl_titanium.c
View File

@ -21,8 +21,6 @@
#include "platinum.h"
DECLARE_GLOBAL_DATA_PTR;
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */

2
board/cavium/thunderx/atf.c
View File

@ -16,8 +16,6 @@
#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size)
{
struct pt_regs regs;

2
board/cei/cei-tk1-som/cei-tk1-som.c
View File

@ -13,8 +13,6 @@
#include "pinmux-config-cei-tk1-som.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs

2
board/compulab/cm_fx6/common.c
View File

@ -15,8 +15,6 @@
#include <fsl_esdhc.h>
#include "common.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \

2
board/compulab/cm_fx6/spl.c
View File

@ -20,8 +20,6 @@
#include <fsl_esdhc.h>
#include "common.h"
DECLARE_GLOBAL_DATA_PTR;
enum ddr_config {
DDR_16BIT_256MB,
DDR_32BIT_512MB,

2
board/compulab/cm_t43/spl.c
View File

@ -14,8 +14,6 @@
#include <power/tps65218.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };

2
board/compulab/common/omap3_display.c
View File

@ -17,8 +17,6 @@
#include <scf0403_lcd.h>
#include <asm/arch-omap3/dss.h>
DECLARE_GLOBAL_DATA_PTR;
enum display_type {
NONE,
DVI,

2
board/dhelectronics/dh_imx6/dh_imx6_spl.c
View File

@ -45,8 +45,6 @@
(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
DECLARE_GLOBAL_DATA_PTR;
static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,

2
board/engicam/common/spl.c
View File

@ -23,8 +23,6 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

2
board/engicam/imx6q/imx6q.c
View File

@ -22,8 +22,6 @@
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \

2
board/engicam/imx6ul/imx6ul.c
View File

@ -22,8 +22,6 @@
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)

2
board/esd/vme8349/pci.c
View File

@ -20,8 +20,6 @@
#include <asm/fsl_i2c.h>
#include "vme8349pin.h"
DECLARE_GLOBAL_DATA_PTR;
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,

2
board/freescale/bsc9131rdb/ddr.c
View File

@ -13,8 +13,6 @@
#include <asm/io.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024

2
board/freescale/bsc9132qds/ddr.c
View File

@ -13,8 +13,6 @@
#include <asm/io.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DDR_RAW_TIMING
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {

2
board/freescale/common/vid.c
View File

@ -17,8 +17,6 @@
#endif
#include "vid.h"
DECLARE_GLOBAL_DATA_PTR;
int __weak i2c_multiplexer_select_vid_channel(u8 channel)
{
return 0;

2
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -38,8 +38,6 @@
#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
DECLARE_GLOBAL_DATA_PTR;
enum {
MUX_TYPE_CAN,
MUX_TYPE_IIC2,

2
board/freescale/ls1088a/eth_ls1088ardb.c
View File

@ -18,8 +18,6 @@
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>
DECLARE_GLOBAL_DATA_PTR;
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)

2
board/freescale/m5329evb/nand.c
View File

@ -13,8 +13,6 @@
#include <asm/io.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>

2
board/freescale/m5373evb/nand.c
View File

@ -13,8 +13,6 @@
#include <asm/io.h>
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>

2
board/freescale/mpc8308rdb/mpc8308rdb.c
View File

@ -20,8 +20,6 @@
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The following are used to control the SPI chip selects for the SPI command.
*/

2
board/freescale/mpc832xemds/pci.c
View File

@ -16,8 +16,6 @@
#include <asm/fsl_i2c.h>
#include "../common/pq-mds-pib.h"
DECLARE_GLOBAL_DATA_PTR;
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,

2
board/freescale/mpc8349emds/pci.c
View File

@ -12,8 +12,6 @@
#include <i2c.h>
#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,

2
board/freescale/mpc8349itx/pci.c
View File

@ -13,8 +13,6 @@
#include <i2c.h>
#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,

2
board/freescale/p1022ds/p1022ds.c
View File

@ -28,8 +28,6 @@
#include "../common/ngpixis.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;

2
board/freescale/p1023rdb/ddr.c
View File

@ -13,8 +13,6 @@
#include <asm/io.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
/* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Hynix H5TQ1G83TFR-H9C

2
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -21,8 +21,6 @@
#include "gsc.h"
#include "common.h"
DECLARE_GLOBAL_DATA_PTR;
#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */

2
board/gdsys/mpc8308/hrcon.c
View File

@ -33,8 +33,6 @@
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
#define MAX_MUX_CHANNELS 2
enum {

2
board/gdsys/mpc8308/strider.c
View File

@ -36,8 +36,6 @@
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
#define MAX_MUX_CHANNELS 2
enum {

2
board/gdsys/p1022/controlcenterd.c
View File

@ -44,8 +44,6 @@
#include "../common/dp501.h"
#include "controlcenterd-id.h"
DECLARE_GLOBAL_DATA_PTR;
enum {
HWVER_100 = 0,
HWVER_110 = 1,

2
board/geekbuying/geekbox/geekbox.c
View File

@ -6,8 +6,6 @@
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;

2
board/intel/edison/edison.c
View File

@ -17,8 +17,6 @@
#include <asm/scu.h>
#include <asm/u-boot-x86.h>
DECLARE_GLOBAL_DATA_PTR;
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.base = CONFIG_SYS_USB_OTG_BASE,

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