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rockchip: boot0: align to 0x20 for armv7 '_start'

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The '_start' is using as vector table base address, and will write
to VBAR register, so it needs to be aligned to 0x20 for armv7.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[Updated to current code base:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Kever Yang 2017-10-10 16:21:02 +02:00 committed by Philipp Tomsich
parent ef70a42f0f
commit cee7470cd8
1 changed files with 12 additions and 2 deletions
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14
arch/arm/include/asm/arch-rockchip/boot0.h
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@ -6,12 +6,13 @@
/*
* Execution starts on the instruction following this 4-byte header
* (containing the magic 'RK33').
* (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This
* magic constant will be written into the final image by the rkimage
* tool, but we need to reserve space for it here.
*
* To make life easier for everyone, we build the SPL binary with
* space for this 4-byte header already included in the binary.
*/
#ifdef CONFIG_SPL_BUILD
/*
* We need to add 4 bytes of space for the 'RK33' at the
@ -26,6 +27,15 @@
b reset /* may be overwritten --- should be 'nop' or a 'b reset' */
#endif
b reset
#if !defined(CONFIG_ARM64)
/*
* For armv7, the addr '_start' will used as vector start address
* and write to VBAR register, which needs to aligned to 0x20.
*/
.align(5)
_start:
ARM_VECTORS
#endif
#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */